search

leonardt / fault

A Python package for testing hardware (part of the magma ecosystem)
BSD 3-Clause "New" or "Revised" License
41 stars 13 forks source link

Imm assert #272

Closed leonardt closed 4 years ago

leonardt commented 4 years ago

Adds support for verilog style immediate assertion syntax

leonardt commented 4 years ago

From http://staging.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-assertions-tutorial/

Immediate assertions are procedural statements and are mainly used in simulation. An assertion is basically a statement that something must be true, similar to the if statement. The difference is that an if statement does not assert that an expression is true, it simply checks that it is true, e.g.:

TLDR; immediate assertions are like if statements that raise an error upon failure (or warning) and the block structure allows you to include other code (so you could run some extra logic to dump state, or something).

Concurrent assertions are built with sequences, so they're fundamentally different in terms of target syntax (immediate: behavioral code inside always block, concurrent: separate syntax based on sequences). I think it's possible to capture the same behavior in both, but it would use different syntax. I'd imagine immediate assertions are simpler for basic software style assertions you're probably familiar with (assert some boolean condition is true, print if message if fail). Concurrent assertions become more useful when you want to write SVA style declarative properties (as opposed to more traditional design style structural/imperative code)