Fault doesn't generate signed inputs when specified through Magma

[zamyers]

(At the request of Steven, I am creating this issue to note a problem I am having.)

I have a block that has several signed unpacked vectors: `module datapath ( input logic signed [constant_gpack::code_precision-1:0] adc_codes [constant_gpack::channel_width-1:0],

input logic clk,
input logic rstb,

output logic signed [ffe_gpack::output_precision-1:0]   estimated_bits_out [constant_gpack::channel_width-1:0],
output logic                                               sliced_bits_out [constant_gpack::channel_width-1:0],
output logic signed [constant_gpack::code_precision-1:0]   est_codes_out [constant_gpack::channel_width-1:0],
output logic signed [error_gpack::est_error_precision-1:0] est_errors_out [constant_gpack::channel_width-1:0],
output logic        [1:0] sd_flags [constant_gpack::channel_width-1:0]

);`

However, when I specify to magma and fault that these input should be signed:

class dut(m.Circuit): name = 'datapath' io = m.IO( clk = m.ClockIn, rstb = m.BitIn, adc_codes = m.In(m.Array[(constant_params['channel_width'], m.SInt[constant_params['code_precision']])]), estimated_bits_out = m.In(m.Array[(constant_params['channel_width'], m.SInt[ffe_params['output_precision']])]), sliced_bits_out = m.In(m.Array[(constant_params['channel_width'], m.SInt[1])]), est_codes_out = m.In(m.Array[(constant_params['channel_width'], m.SInt[constant_params['code_precision']])]), est_errors_out = m.In(m.Array[(constant_params['channel_width'], m.SInt[error_params['est_error_precision']])]), sd_flags = m.In(m.Array[(constant_params['channel_width'], m.SInt[2])]) )

The generated testbench produces unsigned values: reg clk; reg rstb; reg [7:0] adc_codes [15:0]; reg [9:0] estimated_bits_out [15:0]; reg [0:0] sliced_bits_out [15:0]; reg [7:0] est_codes_out [15:0]; reg [8:0] est_errors_out [15:0]; reg [1:0] sd_flags [15:0];

The simulator of choice, ncsim, then complains and throws an error about the signed vs unsigned IO mismatch. I got around this problem by assuming the testbench can only generate unsigned inputs that I then cast into signed ones in my block wrapper.

[leonardt]

Ah, makes sense, it looks like the code to generate the reg to hold the inputs to the test bench isn't checking whether the value is signed. Will look into this.