In verilog, assertions are "behavioral" statements so they need to be
contained within a block such as always or initial (compared to
structural statements such as module instancing or assignment). Before,
we used always @(), however initial is preferred for some tool
compatability an the effect should be the same (since it's an immediate
assertion, it doesn't really make sense to have it sensitive to anything
other than , so we can remove the code related to other events).
In verilog, assertions are "behavioral" statements so they need to be contained within a block such as always or initial (compared to structural statements such as module instancing or assignment). Before, we used always @(), however initial is preferred for some tool compatability an the effect should be the same (since it's an immediate assertion, it doesn't really make sense to have it sensitive to anything other than , so we can remove the code related to other events).