Closed Kuree closed 3 years ago
Generated SV code:
while ((dut.valid) === (0)) begin #5 end
Correct code:
while ((dut.valid) === (0)) begin #5; end
How to reproduce: Run https://github.com/leonardt/magma_examples/blob/master/tests/test_risc.py with "system-verilog".
"system-verilog"
Generated SV code:
Correct code:
How to reproduce: Run https://github.com/leonardt/magma_examples/blob/master/tests/test_risc.py with
"system-verilog"
.