In the verilog simulation, product types are flattened into leaf ports. This adds logic to the monitor code that allows the user to provide a type annotation on an argument that is a product. When encountering product arguments, the observe function will be rewritten to accept the flattened arguments, and a small snippet of code is inserted into the function to reconstruct the original product argument from the flattened arguments. For now, we use SimpleNamespace to provide dot notation on the product fields. In the future, we should figure out a way to pass the magma type converted to hwtypes to the pysv class and use that to reconstruct the original argument.
Support for nested array arguments will be added next.
In the verilog simulation, product types are flattened into leaf ports. This adds logic to the monitor code that allows the user to provide a type annotation on an argument that is a product. When encountering product arguments, the observe function will be rewritten to accept the flattened arguments, and a small snippet of code is inserted into the function to reconstruct the original product argument from the flattened arguments. For now, we use SimpleNamespace to provide dot notation on the product fields. In the future, we should figure out a way to pass the magma type converted to hwtypes to the pysv class and use that to reconstruct the original argument.
Support for nested array arguments will be added next.