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leonardt / fault

A Python package for testing hardware (part of the magma ecosystem)
BSD 3-Clause "New" or "Revised" License
41 stars 13 forks source link

Issue with setting nested arrays #61

Open rsetaluri opened 5 years ago

rsetaluri commented 5 years ago 

Exception ignored in: '_pydevd_frame_eval.pydevd_frame_evaluator_darwin_36_64.get_bytecode_while_frame_eval'
RecursionError: maximum recursion depth exceeded while calling a Python object
RecursionError: maximum recursion depth exceeded while calling a Python object
Exception ignored in: '_pydevd_frame_eval.pydevd_frame_evaluator_darwin_36_64.get_bytecode_while_frame_eval'
RecursionError: maximum recursion depth exceeded while calling a Python object
F
tests/helper_test_readyvalid.py:211 (test_clock_adjusted_2dlb_flicker_ce_with_2x2_stride)
def test_clock_adjusted_2dlb_flicker_ce_with_2x2_stride():
        c = coreir.Context()
        cirb = CoreIRBackend(c)

        testcircuit = DefineTwoDimensionalLineBuffer(cirb, Array(8, In(Bit)), 1, 1, 2, 2, 8, 8, 2, 2, 0, 0, True)

        tester = fault.Tester(testcircuit, testcircuit.CLK)

        for i in range(30):
            if i % 2 == 0:
>               tester.circuit.I[0][0] = int2seq(1, 8)
E               TypeError: 'PortWrapper' object does not support indexing

helper_test_readyvalid.py:222: TypeError
leonardt commented 5 years ago

62 has a preliminary support for setting arrays (see this test https://github.com/leonardt/fault/pull/62/files#diff-be25ab5c75d3019d597f051e308a886cR84), let me know if this fixes the issue.

Can I check out the above test somewhere to try it out? (I'm guessing it's in aetherling, CCing @david-durst)

David-Durst commented 5 years ago

https://github.com/David-Durst/aetherling/blob/2043af4641f5bf46f5dd111d0812acf98f4eb932/tests/helper_test_readyvalid.py#L19-L72

David-Durst commented 5 years ago

Note, in order to run this, you'll need the david-ram-tests magma, mantle, aetherling and fault branches (at least as of 6 pm this evening)

leonardt commented 5 years ago

I had to make the following changes (basically replace int2seq with BitVector).

diff --git a/tests/helper_test_readyvalid.py b/tests/helper_test_readyvalid.py
index 723cb17..215a6f1 100644
--- a/tests/helper_test_readyvalid.py
+++ b/tests/helper_test_readyvalid.py
@@ -233,14 +233,14 @@ def test_clock_adjusted_2dlb_flicker_ce_with_2x2_stride():

     testcircuit = DefineTwoDimensionalLineBuffer(cirb, Array(8, In(Bit)), 1, 1, 2, 2, 8, 8, 2, 2, 0, 0, True)

-    tester = fault.tester(testcircuit, testcircuit.CLK)
+    tester = fault.Tester(testcircuit, testcircuit.CLK)

     for i in range(30):
         if i % 2 == 0:
-            tester.circuit.I[0][0] = int2seq(1, 8)
+            tester.circuit.I[0][0] = BitVector(1, 8)
             tester.circuit.CE = 1
         else:
-            tester.circuit.I[0][0] = int2seq(2, 8)
+            tester.circuit.I[0][0] = BitVector(2, 8)
             tester.circuit.CE = 0

         tester.eval()

It doesn't show the above error on the poke anymore, but now I get the following unconnected port error.

❯ pytest tests/helper_test_readyvalid.py -k test_clock_adjusted_2dlb_flicker_ce_with_2x2_stride
/Users/lenny/miniconda3/lib/python3.7/site-packages/pep8.py:110: FutureWarning: Possible nested set at position 1
  EXTRANEOUS_WHITESPACE_REGEX = re.compile(r'[[({] | []}),;:]')
============================================= test session starts =============================================
platform darwin -- Python 3.7.0, pytest-3.9.3, py-1.7.0, pluggy-0.8.0
rootdir: /Users/lenny/repos/aetherling, inifile:
plugins: profiling-1.4.0, pep8-1.0.6, cov-2.6.0, codestyle-1.4.0
collected 7 items / 6 deselected

tests/helper_test_readyvalid.py F                                                                       [100%]

================================================== FAILURES ===================================================
_____________________________ test_clock_adjusted_2dlb_flicker_ce_with_2x2_stride _____________________________

    def test_clock_adjusted_2dlb_flicker_ce_with_2x2_stride():
        scope = Scope()
        c = coreir.Context()
        cirb = CoreIRBackend(c)

        testcircuit = DefineTwoDimensionalLineBuffer(cirb, Array(8, In(Bit)), 1, 1, 2, 2, 8, 8, 2, 2, 0, 0, True)

        tester = fault.Tester(testcircuit, testcircuit.CLK)

        for i in range(30):
            if i % 2 == 0:
                tester.circuit.I[0][0] = BitVector(1, 8)
                tester.circuit.CE = 1
            else:
                tester.circuit.I[0][0] = BitVector(2, 8)
                tester.circuit.CE = 0

            tester.eval()

            # for some reason, lb going to 0 when flickering valid on and off for ce
            for r in range(2):
                for c in range(2):
                    if i >= 21:
                        tester.circuit.O[0][r][c].expect(1)
>       tester.compile_and_run("coreir")

tests/helper_test_readyvalid.py:253:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
../fault/fault/tester.py:175: in compile_and_run
    self.run(target)
../fault/fault/tester.py:165: in run
    self.targets[target].run(self.actions)
../fault/fault/magma_simulator_target.py:40: in run
    simulator = self.backend_cls(self.circuit, self.clock)
../magma/magma/simulator/coreir_simulator.py:140: in __init__
    coreir_.compile(circuit, coreir_filename, context=self.ctx)
../magma/magma/backend/coreir_.py:450: in compile
    backend.compile(main)
../magma/magma/backend/coreir_.py:424: in compile
    self.compile_dependencies(defn_or_declaration)
../magma/magma/backend/coreir_.py:413: in compile_dependencies
    self.modules[key.name] = self.compile_definition(key)
../magma/magma/backend/coreir_.py:312: in compile_definition
    self.compile_definition_to_module_definition(definition, module_definition)
../magma/magma/backend/coreir_.py:279: in compile_definition_to_module_definition
    output_ports)
../magma/magma/backend/coreir_.py:289: in connect_input
    self.connect(module_definition, port, port.value(), output_ports)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

self = <magma.backend.coreir_.CoreIRBackend object at 0x11860aeb8>
module_definition = <coreir.module.ModuleDef object at 0x118248e80>, port = dehydrate_tArray_8_In_Bit__.out
value = None
output_ports = {dehydrate_tArray_8_In_Bit__.in: 'self.in', dehydrate_tArray_8_In_Bit__.in[0]: 'self.in.0', dehydrate_tArray_8_In_Bit__.in[1]: 'self.in.1', dehydrate_tArray_8_In_Bit__.in[2]: 'self.in.2', ...}

    def connect(self, module_definition, port, value, output_ports):
        self.__unique_concat_id

        # allow clocks or arrays of clocks to be unwired as CoreIR can wire them up
        def is_clock_or_nested_clock(p):
            if isinstance(p, (ClockType, ClockKind)):
                return True
            elif isinstance(p, (ArrayType, ArrayKind)):
                return is_clock_or_nested_clock(p.T)
            elif isinstance(p, (TupleType, TupleKind)):
                for item in p.Ts:
                    if is_clock_or_nested_clock(item):
                        return True
            return False

        if value is None and is_clock_or_nested_clock(port):
            return
        elif value is None:
>           raise Exception(f"Got None for port '{port.debug_name}', is it "
E           Exception: Got None for port 'dehydrate_tArray_8_In_Bit__.out', is it connected to anything?

../magma/magma/backend/coreir_.py:334: Exception
-------------------------------------------- Captured stdout call ---------------------------------------------
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dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
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dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
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dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
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dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) I False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
dict_keys(['AnyDimensionalLineBuffer_Array_8_In_Bit__type__1_1_pxPerClock__2_2_window__8_8_img__2_2_stride__0_0_origin_inst0', 'DelayedBuffer_Array_2_Array_2_Array_8_In_Bit____t_4n_1k_16emittingPeriod_0initialDelay_inst0', 'Counter1_Mod2CE_inst0', 'coreir_const10_inst0', 'coreir_eq_1_inst0', 'and_inst0', 'or_inst0', 'and_inst1', 'or_inst1', 'and_inst2']) O False
=================================== 1 failed, 6 deselected in 4.91 seconds ====================================
leonardt commented 5 years ago

(Edited the above diff to simplify it, my search and replace touched other parts of the file that weren't of interest)