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lerwys / bpm-sw-old-backup

Main repository for the BPM firmware and software
GNU Lesser General Public License v3.0
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[dsp-devel][fmc516] ADC Data appears to be off by one cycle #19

Open lerwys opened 11 years ago

lerwys commented 11 years ago

The ADC data channels 1 and 2 seems to be 1 clock out of sync with data channels 0 and 3.

lerwys commented 11 years ago

Thais was fixed with a programmable delay per channel basis. However, the reason why this happens needs to be further investigated.

lerwys commented 11 years ago

Probably this has something to do with the synchronization between data paths clocked with different clock sources. There is a need to implement an adc_sync_chains modules.

The main reason to do this is because there is an uncertainty associated to each data path. Every time the board is powered-on or the PLL/MMCM looses lock we don't know which datapath will be delayed relative to the each other.