[ddr3-core] Implement a DDR3 core wrapper for Xilinx MIG

[lerwys]

It is necessary a wishbone wrapper to Xilinx MIG generated core.

In this way, we can store the large ammounts of DSP data.

useful links:

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf http://www.ohwr.org/projects/ddr3-sp6-core/wiki

[lerwys]

See http://www.xilinx.com/support/documentation/ip_documentation/mpmc.pdf page 62 onwards for geenrating MPMC in non-EDK based systems.

There is no facility like the one used in http://www.ohwr.org/projects/ddr3-sp6-core (Memory Controller Block) for Virtex-6.

[lerwys]

New document (MIG + AXI interconnect): http://www.xilinx.com/support/documentation/application_notes/xapp788-7-series-axi-mpmc-planahead.pdf

[lerwys]

It was taken a different approach for this problem.

No Wishbone wrapper was implemented or the DDR3 core, as it is provided by the PCIe core and we just need to itnerface it with a common UI interface from Xilinx.

In the future we may change this interface to a Wishbone one or even a custom, simpler one.