[feature] Adding SystemVerilog support

[canesche]

Tasks;

• [x] add SystemVerilog simulator
• [x] add circuit print
• [x] add stats of the circuit (number of wires, regs, memory, ...)
• [ ] add waveform
• [x] add an example of Google Colab usage: link

[pe8sutd]

great to have SystemVerilog!