fpga: improve signal mux

The WonderTANG uses a multiplexing scheme to read 24 signals using just 8 pins through three 74LVC245 ICs.

The multiplexing scheme is driven by a ~108MHz clock (~9.25ns period) using the following schedule based on a 8 cycle plan:

the first cycle is used to select A0-A7 signals and enable signal propagation (which is Ten=~4.4ns for the 74LVC245)
during the second cycle A0-A7 data can be read consistently
the third cycle is used to select A8-A15 signals and enable signal propagation
during the fourth cycle A8-A15 data can be read consistently
the fifth cycle is used to select MERQ,IORQ,CS1,CS2,RESET,RFSH,CS12 and M1 signals and enable signal propagation
during the sixth cycle MERQ,IORQ,CS1,CS2,RESET,RFSH,CS12 and M1 can be read consistently
during the seventh and eighth cycles no signals are selected and the bus is marked idle

This multiplexing scheme seems to work fine for most MSX machines, except for the Omega Home Computer which experiences signal inconsistencies during the multiplexing phase. The root cause of these inconsistencies is not confirmed.

The modification presented here implements a different multiplexing scheme that has been tested successfully both on the Omega Home Computer and other MSX machines.

The same ~108MHz clock is used, but the schedule is changed slightly using a 7 cycle plan:

the first cycle is used to select A0-A7 signals and enable signal propagation
during the second cycle A0-A7 data can be read consistently
the third cycle is used to select A8-A15 signals and enable signal propagation
during the fourth cycle A8-A15 data can be read consistently
the fifth cycle is used to select MERQ,IORQ,CS1,CS2,RESET,RFSH,CS12 and M1 signals and enable signal propagation
during the sixth cycle MERQ,IORQ,CS1,CS2,RESET,RFSH,CS12 and M1 can be read consistently
during just the seventh cycle no signals are selected and the bus is marked idle

lfantoniosi / WonderTANG

fpga: improve signal mux #15