sd_reader and BUFG - Githubissues

Hi! I wonder if I could use the sd_reader module on a TN9K. The SD card pinout on the 20K has a different pin configuration. What do you think?

Another question is, is BUFG verilog instruction available even on VHDL? Is it a native language feature?

Do you know any specific hardware issues on 9K that motivated you to switch to the 20K model?

Nice job, thanks.

Yes it should work just set map the correct pins.

I don’t know why you want to make a new design in VHDL but yet they are there. Go for gowin bufg on google and get the pdf from gowin. You l need to declare the module.

On Mon, Nov 13, 2023 at 10:58 PM Saverio Russo @.***> wrote:

Hi! I wonder if I could use the sd_reader module on a TN9K. The SD card pinout on the 20K has a different pin configuration. What do you think?

Another question is, is BUFG verilog instruction available even on VHDL? Is it a native language feature?

Nice job, thanks.

— Reply to this email directly, view it on GitHub https://github.com/lfantoniosi/WonderTANG/issues/5, or unsubscribe https://github.com/notifications/unsubscribe-auth/ACCJWU7RYFVLHGRB7T3TNMTYEMJAPAVCNFSM6AAAAAA7KJWXDWVHI2DSMVQWIX3LMV43ASLTON2WKOZRHE4TEMJQHEYTMMQ . You are receiving this because you are subscribed to this thread.Message ID: @.***>

Yes it should work just set map the correct pins. I don’t know why you want to make a new design in VHDL but yet they are there. Go for gowin bufg on google and get the pdf from gowin. You l need to declare the module. … On Mon, Nov 13, 2023 at 10:58 PM Saverio Russo @.> wrote: Hi! I wonder if I could use the sd_reader module on a TN9K. The SD card pinout on the 20K has a different pin configuration. What do you think? Another question is, is BUFG verilog instruction available even on VHDL? Is it a native language feature? Nice job, thanks. — Reply to this email directly, view it on GitHub <#5>, or unsubscribe https://github.com/notifications/unsubscribe-auth/ACCJWU7RYFVLHGRB7T3TNMTYEMJAPAVCNFSM6AAAAAA7KJWXDWVHI2DSMVQWIX3LMV43ASLTON2WKOZRHE4TEMJQHEYTMMQ . You are receiving this because you are subscribed to this thread.Message ID: @.>

Thank for quick reply. I'm not familiar with verilog but 15 years of vhdl. Not yet converted myself to verilog or system verilog.

About SD card, the 9K has only 4 pins connected as far as I saw on the schematic and the DAT1 and DAT2 are not connected. I don't know if they must be connected to switch to SDIO instead SPI (do your sd_reader uses SDIO ?).

Btw have you faced some design flaw in 9K board? I don't know why but looks a bit noisy.

The sd reader uses sdbus, no spi. It's derived from the sd_reader from internet i just added write routines to it. Some people reported success using the internet sd reader for 9k so using my version should not be a problem.

The design flaw is to have HDMI EDID vcc connected to the board VCC.

On Tue, Nov 14, 2023 at 4:27 AM Saverio Russo @.***> wrote:

Yes it should work just set map the correct pins. I don’t know why you want to make a new design in VHDL but yet they are there. Go for gowin bufg on google and get the pdf from gowin. You l need to declare the module. … <#m2123692804542791328> On Mon, Nov 13, 2023 at 10:58 PM Saverio Russo @.> wrote: Hi! I wonder if I could use the sd_reader module on a TN9K. The SD card pinout on the 20K has a different pin configuration. What do you think? Another question is, is BUFG verilog instruction available even on VHDL? Is it a native language feature? Nice job, thanks. — Reply to this email directly, view it on GitHub <#5 https://github.com/lfantoniosi/WonderTANG/issues/5>, or unsubscribe https://github.com/notifications/unsubscribe-auth/ACCJWU7RYFVLHGRB7T3TNMTYEMJAPAVCNFSM6AAAAAA7KJWXDWVHI2DSMVQWIX3LMV43ASLTON2WKOZRHE4TEMJQHEYTMMQ https://github.com/notifications/unsubscribe-auth/ACCJWU7RYFVLHGRB7T3TNMTYEMJAPAVCNFSM6AAAAAA7KJWXDWVHI2DSMVQWIX3LMV43ASLTON2WKOZRHE4TEMJQHEYTMMQ . You are receiving this because you are subscribed to this thread.Message ID: @.>

Thank for quick reply. I'm not familiar with verilog but 15 years of vhdl. Not yet converted myself to verilog or system verilog.

About SD card, the 9K has only 4 pins connected as far as I saw on the schematic and the DAT1 and DAT2 are not connected. I don't know if they must be connected to switch to SDIO instead SPI (do your sd_reader uses SDIO ?).

Btw have you faced some design flaw in 9K board? I don't know why but looks a bit noisy.

— Reply to this email directly, view it on GitHub https://github.com/lfantoniosi/WonderTANG/issues/5#issuecomment-1810111130, or unsubscribe https://github.com/notifications/unsubscribe-auth/ACCJWU2ANTY2NSIJTDPSL5DYENPRZAVCNFSM6AAAAAA7KJWXDWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQMJQGEYTCMJTGA . You are receiving this because you commented.Message ID: @.***>

-- Luis Felipe Antoniosi

Probably I will switch to 20K as well, I don't realize if my code isn't good or it's a board issue. I need to learn verilog, looks like similar to c-like languages. I found all documents about gowin primitives thank you.

I used to coding on altera FPGA before the prices rose up

Il mer 15 nov 2023, 09:51 lfantoniosi @.***> ha scritto:

The sd reader uses sdbus, no spi. It's derived from the sd_reader from internet i just added write routines to it. Some people reported success using the internet sd reader for 9k so using my version should not be a problem.

The design flaw is to have HDMI EDID vcc connected to the board VCC.

On Tue, Nov 14, 2023 at 4:27 AM Saverio Russo @.***> wrote:

Yes it should work just set map the correct pins. I don’t know why you want to make a new design in VHDL but yet they are there. Go for gowin bufg on google and get the pdf from gowin. You l need to declare the module. … <#m2123692804542791328> On Mon, Nov 13, 2023 at 10:58 PM Saverio Russo @.*> wrote: Hi! I wonder if I could use the sd_reader module on a TN9K. The SD card pinout on the 20K has a different pin configuration. What do you think? Another question is, is BUFG verilog instruction available even on VHDL? Is it a native language feature? Nice job, thanks. — Reply to this email directly, view it on GitHub <#5 https://github.com/lfantoniosi/WonderTANG/issues/5>, or unsubscribe

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Thank for quick reply. I'm not familiar with verilog but 15 years of vhdl. Not yet converted myself to verilog or system verilog.

About SD card, the 9K has only 4 pins connected as far as I saw on the schematic and the DAT1 and DAT2 are not connected. I don't know if they must be connected to switch to SDIO instead SPI (do your sd_reader uses SDIO ?).

Btw have you faced some design flaw in 9K board? I don't know why but looks a bit noisy.

— Reply to this email directly, view it on GitHub < https://github.com/lfantoniosi/WonderTANG/issues/5#issuecomment-1810111130>,

or unsubscribe < https://github.com/notifications/unsubscribe-auth/ACCJWU2ANTY2NSIJTDPSL5DYENPRZAVCNFSM6AAAAAA7KJWXDWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQMJQGEYTCMJTGA>

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-- Luis Felipe Antoniosi

— Reply to this email directly, view it on GitHub https://github.com/lfantoniosi/WonderTANG/issues/5#issuecomment-1812036779, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABZCLIF4PSJKG2HGJ5PV5KDYER7CDAVCNFSM6AAAAAA7KJWXDWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQMJSGAZTMNZXHE . You are receiving this because you authored the thread.Message ID: @.***>

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sd_reader and BUFG #5