Incompatibility with the latest GOWIN FPGA Designer 1.9.9 Beta4

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Incompatibility with the latest GOWIN FPGA Designer 1.9.9 Beta4 #8

Open cristianoag opened 9 months ago

cristianoag commented 9 months ago

Be aware that the Verilog/VHDL code synthetizes but the Place & Route phase (Floor Planning) cannot complete on the latest GowinSemi FPGA Designer educational version. There ar eincompatibilities with the memory management that blocks that version to finish the process. Download and use the 1.9.8.11 version from https://cdn.gowinsemi.com.cn/Gowin_V1.9.8.11_Education_win.zip

herraa1 commented 4 months ago

I can confirm that this was fixed in commit 5715d2c "support to Gowin Beta 1.9.9 Beta-4" so this issue can be closed.