search

li3tuo4 / rc-fpga-zcu

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
Other
57 stars 15 forks source link

FESVR with 32-bit configuration #7

Closed shivampotdar closed 2 years ago

shivampotdar commented 3 years ago

Thank you for your contribution in making this work public.

I was trying to generate a RV32 variant of RocketChip on ZCU102. I created a new configuration in RocketChip Configs.scala and with changing width-related parameters (manually) from 64 to 32 in testchipip. This generates the bitstream and ARM Linux can boot. I recompiled fesvr-zynq and pk (from your riscv-pk-zcu repo) (not trying bbl at the moment) with SiFive toolchain. All this flow works but when I try to run the program with ./fesvr_zynq, no output is obtained. It is non hanging the whole system either as Ctrl+C works.

What could I be missing on?

li3tuo4 commented 3 years ago

Hi shivampotdar,

I have no experience with RV32 config yet. If ./fesvr_zynq hangs, it's usually something wrong in the connection between PS and PL. From my understanding, the correctness of top-level wrapper hardware might be affected, assuming RV32's memory bus will be 32-bit wide. There is one line connecting the rocket chip's memory bus to the host ARM processor. This wire also re-maps the address bit according to the address space in the host processor (PS) side. Check if that mapping is still valid for your current 32-bit memory bus.

Good luck, Tuo