AG1280q48 tutorial

[gabonator]

Hello, do you have any follow up on this topic? https://oshwhub.com/libc0607/ag1280q48-demo-v1

I am looking for a toolchain for building fpga bitstream for AGL1K used in Miniware DS213 and LA104. Would it be possible to migrate the page here on github?

[libc0607]

Hello, do you have any follow up on this topic? https://oshwhub.com/libc0607/ag1280q48-demo-v1

I am looking for a toolchain for building fpga bitstream for AGL1K used in Miniware DS213 and LA104. Would it be possible to migrate the page here on github?

Sorry I'm just now noticing this comment due to incorrect notification settings

I've uploaded all the documents about AGM FPGAs that I could find on the Chinese Internet to a Telegram channel, see https://t.me/agmfpgadoc

[gabonator]

Wow, quite a load of resources! It will take me some time to go through it. Based on your webpage I was able to move forward and this is what I have found out:

• reverse engineering of encryption algorithm alta-gate supra uses, I was hoping to find something that would help me configuring SPI interface, since there is no documentation on this: https://github.com/gabonator/Education/tree/master/2021/AltaGateReverse
• Standalone toolchain (supra + quartus) in single zipped archive. Just by running one bat file, it will compile the verilog into bitstream. Quartus was slighlty modified to extend its trial period. Whole package has just 428MB (quartus + cyclone support files + supra), I removed a lot of files which were not used during verilog building. https://github.com/gabonator/LA104/discussions/81
• verification toolchain running on LA104. Each verilog application is paired with simple testing application in C++ which can be built and run either locally on your pc to verify your verilog code (using verilator) or can be built for ARM (on LA104) which does the same but with real fpga chip: https://github.com/gabonator/LA104/tree/master/system/apps/123_fpga

[libc0607]

Your work on LA104 is great.

Also, I'm interested in how Supra's file encryption works. I had found some research of its encryption here on pablomarx/rodinia, but my own attempts were unsuccessful.

Supra also has a Linux version, but it looks like not every version has been released. Version 2019.10.b0-aea55308 uploaded in the Telegram channel is the latest version I could find. It contains a yosys executable and provides the synth_agm command, but I haven't tested whether it works . This might be useful for building standalone toolchain under Linux. I didn't download all the versions due to the speed limit of pan.baidu.com, if other versions of Supra needed I can upload them.

The timing of using AG1K as SPI Slave for bitstream configuration is mentioned in "MANUAL_AG1KLP.pdf" (the figure below). I have also tried to use SPI to load bitstream (code is here), this code receives the .bin generated by Supra from the USB and writes it to the AG1K via the SPI interface.

[gabonator]

Now I feel really stupid since someone did the same reverse engineering 3 years ago, so I was just wasting my time :) I downloaded all files from your telegram channel, look through all documents carefully but I couldn't find any piece of code or example how to configure the SPI for runtime communication with MCU. Not for flashing, this part works well in my project. Currently I am using custom software implemented SPI interface to talk to MCU, but its speed is quite low. I am still beginner with verilog, co it could be possibly optimized for higher speed, but I am sure that internal SPI interface can be somehow configured to use it for high speed bidirectional communication with internal peripheral. Thank you very much for valuable resources anyway. Just tried linux version of supra, and it works like a charm!

[gabonator]

I am working on docker container for synthesising AGM FPGA streams. I have everything working - linux docker image is running with simple nodejs script which creates web server waiting for verilog files sent as attachment. Two CURL requests are necessary to create bitstream. First one starts the quartus synthesis and supra conversions and returns stdout stream from all executed tools to see all output messages. When this one is finished, you need to call another CURL which returns the resulting bitstream. See the last image on this page for reference: https://github.com/gabonator/LA104/tree/master/system/apps_featured/133_fpgawave

All of this takes only 800 MB and the only missing piece to design standalone docker image is the download url for Supra (linux build), is there any chance that the Supra-2019.10.b0-aea55308-all.tar.gz is hosted somewhere on public server? I know that you posted it in your telegram channel, but there is no easy way how to download it from there within bash script.

[libc0607]

Maybe I can create a repo, and upload it to the "release"? But it would be better to ask AGM for their opinion and this should have been done by them.

[libc0607]

It seems that AGM has started to pay attention to individual users and overseas markets since the start of this year. Good news.

I just mentioned the Supra and chip documentation to the AGM salesman, and his reply:

1. They recently started a website (http://www.agmcu.com) for oversea users. Currently they have uploaded MCU (AGRV/AG32 series) documents, and uploaded the PlatformIO SDK to Github (https://github.com/AGMCU).
2. They are discussing how to release the Supra - not for long I guess?
3. Quartus is still needed for logic synthesis, Supra is only used for map, place & route; other functions in Supra (e.g. the synth_agm command in yosys built-in) are in an unmaintained state.
4. Since there are very few Linux desktop users in China, they have not updated the Linux version of Supra in recent years. But he will provide feedback to the technical and continue to update the Linux version of Supra in the future.