[ga-945gcm-s2l] Can the FSB be overclocked to 1333MHz?

[ghost]

According to Gigabyte, the vendor BIOS is able to overclock the FSB to 1333MHz. If coreboot can do the same, we would be able to use Core 2 Duo E8xxx chips on these boards.

[ghost]

kevin@test-machine:~$ sudo i2cdetect -l
i2c-0        smbus             SMBus I801 adapter at 0400              SMBus adapter
i2c-1        i2c               i915 gmbus ssc                          I2C adapter
i2c-2        i2c               i915 gmbus vga                          I2C adapter
i2c-3        i2c               i915 gmbus panel                        I2C adapter
i2c-4        i2c               i915 gmbus dpc                          I2C adapter
i2c-5        i2c               i915 gmbus dpb                          I2C adapter
i2c-6        i2c               i915 gmbus dpd                          I2C adapter

kevin@test-machine:~$ sudo i2cdetect 0
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0.
I will probe address range 0x03-0x77.
Continue? [Y/n] y
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- 08 -- -- -- -- -- -- -- 
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 
50: 50 -- 52 -- -- -- -- -- -- -- -- -- -- -- -- -- 
60: -- -- -- -- -- -- -- -- -- 69 -- -- -- -- -- -- 
70: -- -- -- -- -- -- -- --    

[ArthurHeymans]

The voltage controller is at offset 0x69, no datasheets about it. This will not be a trivial task.

[zamaudio]

I've come across 0x69 before in pineview, I think its a CK505 clock generator chip there is a doc somewhere online for this. Is this it: http://zamaudio.com/mbox2/ck505.pdf

[zamaudio]

I used something like the following: Make sure to get the correct values for yours on the datasheet or even by reading the existing values.

+#define SMB_CKxxx  0x69
+#define  SMB_CMD   0
+
+   int i, ret;
+   // CHANGE THIS TO SUIT
+   u8 wbuf[13] = { 0x61, 0xd9, 0xfe, 0xff, 0xff, 0x00, 0x00,
+           0x01, 0x03, 0x25, 0x83, 0x17, 0x0d};
+   u8 rbuf[13] = { 0 };
+   u16 count = 13;
+   printk(BIOS_SPEW, "Reading CKxxx clock chip config : ");
+   count = smbus_block_read(SMB_CKxxx, SMB_CMD, count, rbuf);
+   for (i = 0; i < 13; i++) {
+       printk(BIOS_SPEW, "%02x ", rbuf[i]);
+   }
+   if (count == 13) {
+       printk(BIOS_SPEW, "done\n");
+
+       printk(BIOS_SPEW, "Writing CKxxx clock chip config : ");
+       ret = smbus_block_write(SMB_CKxxx, SMB_CMD, count, wbuf);
+       if (!ret) {
+           for (i = 0; i < 13; i++) {
+               printk(BIOS_SPEW, "%02x ", wbuf[i]);
+           }
+           printk(BIOS_SPEW, "done\n");
+       } else {
+           printk(BIOS_SPEW, "failed\n");
+       }
+   } else {
+       printk(BIOS_SPEW, "failed\n");
+   }

--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -55,3 +55,13 @@ int smbus_read_byte(unsigned device, unsigned address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
+
+int smbus_block_read(unsigned device, unsigned cmd, unsigned bytes, u8 *buf)
+{
+   return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}
+
+int smbus_block_write(unsigned device, unsigned cmd, unsigned bytes, u8 *buf)
+{
+   return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index d4adc18..03719ab 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -48,6 +48,8 @@ void gpi_route_interrupt(u8 gpi, u8 mode);
 #else
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
+int smbus_block_read(unsigned device, unsigned cmd, unsigned bytes, u8 *buf);
+int smbus_block_write(unsigned device, unsigned cmd, unsigned bytes, u8 *buf);
 int southbridge_detect_s3_resume(void);
 #endif
 #endif

[ghost]

Seeing how incredibly the x4x code has impoved over the last months, I don't think it's worthwhile to do this on i945 any more. x4x supports FSB1333 natively and is better in all aspects.

i945 does not support quad cores anyway, so only a limited amount of new cpu's would have been supported by this.