Refactor fpga logic - Githubissues

librecores / riscv-sodor

educational microarchitectures for risc-v isa

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Refactor fpga logic #5

Closed codelec closed 6 years ago

codelec commented 6 years ago

Logic employed for the following needs to be simplified

[x] 3stage -> send memory request only once
[x] rv32_3stage/frontend.scala
[x] fpgatop/top.scala -> add some comments to existing tests
[x] rv32_3stage/dpath.scala -> hazard stall logic, fcn signal of data mem port
[x] rv32_*/package.scala
[x] common/debug.scala

In the current branch related to the fpga logic if you find something not understandable please comment in this issue