Q0 register support for ARMv7

lifting-bits / anvill

anvill forges beautiful LLVM bitcode out of raw machine code

GNU Affero General Public License v3.0

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Q0 register support for ARMv7 #276

Open artemdinaburg opened 2 years ago

artemdinaburg commented 2 years ago

The anghabench test armv7/python/success/FFmpeg/libavformat/extr_libmodplug.c_modplug_read_packet.elf/output.json is failing due to:

Unable to decode 0th function in 'functions' list of program specification: Could not parse 3th parameter of function at address 0: Unable to locate register 'Q0' used for storing function parameter

We should support this in remill/anvill or work around it, if not needed.

sschriner commented 2 years ago

To follow up with this: Adding Q0 register support is a subtask within the larger task of supporting vector, SIMD, and FP instructions in ARMv7 and Thumb2 (for both remill and anvill)

sschriner commented 2 years ago

So we need to support a few more registers for that than Q0. (I can comprise a complete list a bit later).

2over12 commented 2 years ago

As a workaround for now I'm allowing parsing to continue when a function spec fails to parse #294