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lifting-bits / remill

Library for lifting machine code to LLVM bitcode
Apache License 2.0
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Update Instruction.cpp to account for ARMv7 shifting into carry out #534

Closed sschriner closed 3 years ago

sschriner commented 3 years ago

Addresses the following edge case in a few places:

<amount>   For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR)
           or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.