Verilog Parser Fails When Port Declaration is in Module Definition

[AndruePeters]

OriginalInput

module AOI (input A, B, C, D, output F);
  assign F = ~((A & B) | (C & D));
endmodule

Output from test_bison.cpp

////////////// test1 ////////////////
VerilogDataBase::VerilogDataBase
ultrasimple.v:2.13-17: syntax error, unexpected INPUT, expecting NAME or ')'
////////////// test2 ////////////////
VerilogDataBase::VerilogDataBase
ultrasimple.v:2.13-17: syntax error, unexpected INPUT, expecting NAME or ')'

However, if we change it to:
module AOI (A, B, C, D, F);
  input A;
  output F;
  assign F = ~((A & B) | (C & D));
endmodule

Then it succeeds (kind of). Not sure why it's reporting this error:

////////////// test1 ////////////////
VerilogDataBase::VerilogDataBase
verilog_module_declaration_cbk => AOI
        A[-2147483648:-2147483648]      B[-2147483648:-2147483648]      C[-2147483648:-2147483648]      D[-2147483648:-2147483648]      F[-2147483648:-2147483648]
verilog_pin_declare_cbk => A 1 (-2147483648, -2147483648)
verilog_pin_declare_cbk => F 2 (-2147483648, -2147483648)
ultrasimple.v:5.15: syntax error, unexpected $undefined, expecting NAME
////////////// test2 ////////////////
VerilogDataBase::VerilogDataBase
verilog_module_declaration_cbk => AOI
        A[-2147483648:-2147483648]      B[-2147483648:-2147483648]      C[-2147483648:-2147483648]      D[-2147483648:-2147483648]      F[-2147483648:-2147483648]
verilog_pin_declare_cbk => A 1 (-2147483648, -2147483648)
verilog_pin_declare_cbk => F 2 (-2147483648, -2147483648)
ultrasimple.v:5.15: syntax error, unexpected $undefined, expecting NAME

[limbo018]

Hi, Thanks for using Limbo.

The current verilog parser only support gate-level netlist syntax. I don't think it is easy to handle behavioral verilog.

For example, the gate-level syntax includes, AND inst (.a(net1), .b(net2)); AND inst (net1, net2); or simple assignment assign A = B; assign A = B[1:10];

Come back to the problem you raise. I expect both cases should fail, as such logic computation in the assignment expression is not supported.

[AndruePeters]

Gotcha. I didn't realize that about the assignments for this parser.

The issue I was trying to demonstrate is still on the structural side. This is the problem with the module definitions when input or output is specified in the port list.

module AOI (input A, B, C, D, output F);
   assign F = A;
endmodule

This fails because of the port list. It's still structural. I've seen (and have) a lot of test articles that use this syntax, and you definitely have one of the better open source parsers I've seen so far. I could probably write a script to change the port lists in the definition for myself, though.

[limbo018]

I have added support for syntax with input/output declared with the module parameters.

See commit 41b9453

[AndruePeters]

Awesome. Thank you. I was starting to write one in X3, but this saves a lot of prototyping time.