Switching to ARM Generic timers solves these problems:
Avoid any collisions with linux kernel perf subsystem when using PMU
as a tick source. Although perf subystem has a kernel
API(perf_event_create_kernel_counter etc.), unfortunately it doesn't
have any capabilites to enable EL0 access to cycle counter on
armv7/armv8 architectures (only for x86 platforms, where it's possible
to set bit which permits executing rdtsc from usermode)
Avoid any conditions, when frequency scaling occurs (moslty different
power states), or core is in wait-for-interrupt/wait-for-events states
(PMU doesn't count CPU cycles in these states).
Common tick source for all cores with fixed frequency
PL1 physical timer runs at frequency typically in the range 1-50MHz.
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Switching to ARM Generic timers solves these problems:
PL1 physical timer runs at frequency typically in the range 1-50MHz.
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>