[at91bootstrap][PATCH] driver: at91_slowclk: do not overwrite valid slow clk settings

[ademers-axceta]

If slow clk settings are already good on boot, it means the VDDBU power was kept during the whole poweroff period, and thus the slow clock is functionnal. There is no need to reconfigure it.

This fixes an issue where some boards got bricked when power is lost during the configuration of the slow clock. There is a race condition underneath the logic of slowclk_switch_osc32() which causes all slow clock sources to be disabled if power is lost during the clock source switch.

slowclk_switch_osc32 will now avoid the clock source switching if it is not necessary.

[LiBinSHA]

Thanks, it was merged to 97de6b88eb23512d89907bbbc9e63bb37458dc45