See if we can implement "topdown" perf event support

[mpe]

See:

• a39fcae7a836 ("perf/x86/intel: Add topdown events to Intel Core")
• 239bd47f8355 ("perf stat: Add computation of TopDown formulas")

topdown level 1 uses a set of abstracted metrics which are generic to out of order CPU cores (although some CPUs may not implement all of them):

topdown-total-slots Available slots in the pipeline topdown-slots-issued Slots issued into the pipeline topdown-slots-retired Slots successfully retired topdown-fetch-bubbles Pipeline gaps in the frontend topdown-recovery-bubbles Pipeline gaps during recovery from misspeculation

A slot is a single operation in the CPU pipe line.

These metrics then allow to compute four useful metrics: FrontendBound, BackendBound, Retiring, BadSpeculation.

[maddy-kerneldev]

Here is the paper that explains further https://6f194736-a-62cb3a1a-s-sites.googlegroups.com/site/analysismethods/yasin-pubs/TopDown-Yasin-ISPASS14.pdf?attachauth=ANoY7cqvpNTliSxNcOaGSA1atp2fCvj-4-IT4G8fgAI_-B7yafyNhJ25OedHKyXGoiq5w1sbzu876yq9WbbEUNOrb14mYKpPDU2i_x1_PtturOsZgsZxNayjp8YsSlk1NOKZMhj3W7IP1Xy_nUrBxjLDyizuGLUv7eBNapY_eGsb4T204N0nFg-wad6M7emsHcKRa2xYXxDhTVbWhXbg4OlSsKiAf9DdosPexOk6NVXwcES94FD2zLMrusoaDVwQVl09zseQltXN&attredirects=0