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lip6 / coriolis

Coriolis VLSI EDA Tool (LIP6)
https://coriolis.lip6.fr
GNU General Public License v2.0
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Fixed Verilog netlist export with presence of unconnected plugs #96

Closed lanserge closed 7 months ago

lanserge commented 7 months ago

Check added: if unconnected plug returns 0 when plug->getNet() called. Also made port be output by default when net direction undefined.

github-actions[bot] commented 7 months ago

A preview of ee225198afe009ec6bec14917957c1c43c5a173f is uploaded and can be seen here:

✨ https://lip6.github.io/coriolis/pull/96/ ✨

Changes may take a few minutes to propagate. Since this is a preview of production, content with draft: true will not be rendered. The source is here: https://github.com/lip6/coriolis/tree/gh-pages/pull/96/