Wish to provide verilog and systemverilog language plug-ins

[shengqilong]

Hope to provide verilog and systemverilog language plug-ins, support verilog and systemverilog syntax highlighting

[kemzops]

@shengqilong can you test this code snippet ? i wrote it as a concept and requires further testing. report anything back to me.

-- mod-version:3

local syntax = require "core.syntax"

syntax.add {
    name = "Verilog/SystemVerilog",
    files = { "%.v$", "%.sv$" },
    block_comment = { "/*", "*/" },  -- Block comment pattern
    comment = "//",
    patterns = {
        { pattern = "//.*", type = "comment"  },
        { pattern = { "/%*", "%*/" },   type = "comment"  },
        { pattern = { '"', '"', '\\' }, type = "string" },  -- Double quoted string
        { pattern = [=[(['"])(\\\1|.)-%1]=], type = "string" },  -- Single quoted string (there is some issue but it works)
        { pattern = "0[bB][01]+%W", type = "number" },  -- Binary number
        { pattern = "[0-1]+[bB]%W", type = "number" },  -- Binary number
        { pattern = "0[xX][%da-fA-F]+%W", type = "number" },  -- Hexadecimal number
        { pattern = "%x+[hH]%W", type = "number" },  -- Hexadecimal number
        { pattern = "%d+[%d%.eE]*f?", type = "number" },  -- Floating point number
        { pattern = "%.?%d+f?", type = "number" },  -- Floating point number
        { pattern = "%%+[%a_][%w_]*", type = "keyword2" },  -- SystemVerilog macros
        { pattern = "[%+%-=/%*%^%%<>!~|&%$]", type = "operator" },  -- Operators
        { pattern = "[%a_][%w_]*:%W", type = "function" },  -- Labels
        { pattern = "[%a_][%w_]*", type = "symbol" },  -- Symbols/Identifiers
        { pattern = "%.%.%a+", type = "normal" }  -- Preprocessor directives
    },
    symbols = {
        -- Verilog/SystemVerilog keywords
        ["always"] = "keyword",
        ["and"] = "keyword",
        ["assign"] = "keyword",
        ["automatic"] = "keyword",
        ["begin"] = "keyword",
        ["case"] = "keyword",
        ["casex"] = "keyword",
        ["casez"] = "keyword",
        ["cell"] = "keyword",
        ["cmos"] = "keyword",
        ["config"] = "keyword",
        ["deassign"] = "keyword",
        ["default"] = "keyword",
        ["defparam"] = "keyword",
        ["design"] = "keyword",
        ["disable"] = "keyword",
        ["edge"] = "keyword",
        ["else"] = "keyword",
        ["end"] = "keyword",
        ["endcase"] = "keyword",
        ["endconfig"] = "keyword",
        ["endfunction"] = "keyword",
        ["endgenerate"] = "keyword",
        ["endmodule"] = "keyword",
        ["endprimitive"] = "keyword",
        ["endspecify"] = "keyword",
        ["endtable"] = "keyword",
        ["endtask"] = "keyword",
        ["event"] = "keyword",
        ["for"] = "keyword",
        ["force"] = "keyword",
        ["forever"] = "keyword",
        ["fork"] = "keyword",
        ["function"] = "keyword",
        ["generate"] = "keyword",
        ["genvar"] = "keyword",
        ["highz0"] = "keyword",
        ["highz1"] = "keyword",
        ["if"] = "keyword",
        ["ifnone"] = "keyword",
        ["incdir"] = "keyword",
        ["include"] = "keyword",
        ["initial"] = "keyword",
        ["inout"] = "keyword",
        ["input"] = "keyword",
        ["instance"] = "keyword",
        ["integer"] = "keyword",
        ["join"] = "keyword",
        ["large"] = "keyword",
        ["liblist"] = "keyword",
        ["library"] = "keyword",
        ["localparam"] = "keyword",
        ["macromodule"] = "keyword",
        ["medium"] = "keyword",
        ["module"] = "keyword",
        ["nand"] = "keyword",
        ["negedge"] = "keyword",
        ["nmos"] = "keyword",
        ["nor"] = "keyword",
        ["noshowcancelled"] = "keyword",
        ["not"] = "keyword",
        ["notif0"] = "keyword",
        ["notif1"] = "keyword",
        ["or"] = "keyword",
        ["output"] = "keyword",
        ["parameter"] = "keyword",
        ["pmos"] = "keyword",
        ["posedge"] = "keyword",
        ["primitive"] = "keyword",
        ["pull0"] = "keyword",
        ["pull1"] = "keyword",
        ["pulldown"] = "keyword",
        ["pullup"] = "keyword",
        ["pulsestyle_ondetect"] = "keyword",
        ["pulsestyle_onevent"] = "keyword",
        ["rcmos"] = "keyword",
        ["real"] = "keyword",
        ["realtime"] = "keyword",
        ["reg"] = "keyword",
        ["release"] = "keyword",
        ["repeat"] = "keyword",
        ["rnmos"] = "keyword",
        ["rpmos"] = "keyword",
        ["rtran"] = "keyword",
        ["rtranif0"] = "keyword",
        ["rtranif1"] = "keyword",
        ["scalared"] = "keyword",
        ["showcancelled"] = "keyword",
        ["signed"] = "keyword",
        ["small"] = "keyword",
        ["specify"] = "keyword",
        ["specparam"] = "keyword",
        ["strong0"] = "keyword",
        ["strong1"] = "keyword",
        ["supply0"] = "keyword",
        ["supply1"] = "keyword",
        ["table"] = "keyword",
        ["task"] = "keyword",
        ["time"] = "keyword",
        ["tran"] = "keyword",
        ["tranif0"] = "keyword",
        ["tranif1"] = "keyword",
        ["tri"] = "keyword",
        ["tri0"] = "keyword",
        ["tri1"] = "keyword",
        ["triand"] = "keyword",
        ["trior"] = "keyword",
        ["trireg"] = "keyword",
        ["unsigned"] = "keyword",
        ["use"] = "keyword",
        ["vectored"] = "keyword",
        ["wait"] = "keyword",
        ["wand"] = "keyword",
        ["weak0"] = "keyword",
        ["weak1"] = "keyword",
        ["while"] = "keyword",
        ["wire"] = "keyword",
        ["wor"] = "keyword",
        ["xnor"] = "keyword",
        ["xor"] = "keyword",
        -- SystemVerilog additional keywords
        ["alias"] = "keyword",
        ["always_comb"] = "keyword",
        ["always_ff"] = "keyword",
        ["always_latch"] = "keyword",
        ["assert"] = "keyword",
        ["assume"] = "keyword",
        ["before"] = "keyword",
        ["bind"] = "keyword",
        ["bins"] = "keyword",
        ["binsof"] = "keyword",
        ["bit"] = "keyword",
        ["break"] = "keyword",
        ["byte"] = "keyword",
        ["shortint"] = "keyword",
        ["int"] = "keyword",
        ["longint"] = "keyword",
        ["logic"] = "keyword",
        ["shortreal"] = "keyword",
        ["realtime"] = "keyword",
        ["void"] = "keyword",
    }
}

[kemzops]

This code should work, but there may be issues with quotes. I'll check other IDE extensions so maybe i will find better implementation. Let me know if you encounter any problems or have suggestions for improvement.

For reference, you can find more information in the Lite XL documentation creating syntaxes developer guide.

[shengqilong]

Thank you so much, this code does work，but can an expression like 1'b1 be recognized as a number？

[shengqilong]

Thank you so much, this code does work，but can an expression like 1'b1 be recognized as a number？

[shengqilong]

files with .v extension cannot be highlighted，why?

[kemzops]

files with .v extension cannot be highlighted，why?

it should work ? its working for me... and about the number thing, you can update the regex if you wish... check the docs

[PerilousBooklet]

The .v file extension is also for the V programming language files. There may be compatibility issues.