as it is written in the Readme file. Got the following error:
make: Leaving directory '/opt/litex_install/build/sim/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x6084).
INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x6084.
Traceback (most recent call last):
File "/opt/litex_install/litex/litex/tools/litex_sim.py", line 517, in <module>
main()
File "/opt/litex_install/litex/litex/tools/litex_sim.py", line 509, in main
builder.build(
File "/opt/litex_install/litex/litex/soc/integration/builder.py", line 367, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
File "/opt/litex_install/litex/litex/soc/integration/soc.py", line 1307, in build
return self.platform.build(self, *args, **kwargs)
File "/opt/litex_install/litex/litex/build/sim/platform.py", line 57, in build
return self.toolchain.build(self, *args, **kwargs)
File "/opt/litex_install/litex/litex/build/sim/verilator.py", line 258, in build
_compile_sim(build_name, verbose)
File "/opt/litex_install/litex/litex/build/sim/verilator.py", line 166, in _compile_sim
raise OSError("Subprocess failed with {}\n{}".format(p.returncode, "\n".join(error_messages)))
OSError: Subprocess failed with 2
%Error-TIMESCALEMOD: /opt/litex_install/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2)
1 | module IntXbar(
| ^~~~~~~
/opt/litex_install/build/sim/gateware/sim.v:21:8: ... Location of module with timescale
21 | module sim (
| ^~~
as it is written in the Readme file. Got the following error:
Got another error later but it seems to be related to my Verilator 4.110 install (https://github.com/verilator/verilator/issues/2838)