Unable to build rocket cpu for terrasic de2 115

[arunlee77]

Hi,

I am trying litex to generate a rocket based soc for terrasic de2 115.

Command i used to build is:

litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-variant linux --sys-clk-freq 50e6

But it generates the following error

Info (12128): Elaborating entity "plusarg_reader" for hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error (10174): Verilog HDL Unsupported Feature error at plusarg_reader.v(22): system function "$value$plusargs" is not supported for synthesis File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v Line: 22
Error (12152): Can't elaborate user hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 329 warnings
    Error: Peak virtual memory: 852 megabytes
    Error: Processing ended: Wed Oct 11 22:46:26 2023
    Error: Elapsed time: 00:00:33
    Error: Total CPU time (on all processors): 00:00:49
Traceback (most recent call last):
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 90, in <module>
    main()
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 83, in main
    builder.build(**parser.toolchain_argdict)
  File "/home/arun/litex/litex/soc/integration/builder.py", line 367, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/arun/litex/litex/soc/integration/soc.py", line 1332, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/altera/platform.py", line 45, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/generic_toolchain.py", line 123, in build
    self.run_script(script)
  File "/home/arun/litex/litex/build/altera/quartus.py", line 216, in run_script
    raise OSError("Error occured during Quartus's script execution.")
OSError: Error occured during Quartus's script execution.

I am using: Ubuntu 20.04

Quartus:

Quartus Prime Design Software
Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
Copyright (C) 2023  Intel Corporation. All rights reserved.

Does anyone got a clue on what is wrong? Could it be the quartus version? or something else?

regards arun

[gsomlo]

On Thu, Oct 12, 2023 at 12:04:24AM -0700, Arun Ravindran wrote:

Info (12128): Elaborating entity "plusarg_reader" for hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635 Error (10174): Verilog HDL Unsupported Feature error at plusarg_reader.v(22): system function "$value$plusargs" is not supported for synthesis File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v Line: 22 Error (12152): Can't elaborate user hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635 Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 329 warnings

Definitely looks like Quartus dislikes something about the RocketChip Chisel-generated verilog.

I'll defer to anyone who might have successfully used Quartus to build RocketChip in the past, as I have not done so (all I've ever used is vivado and yosys/trellis/nextpnr on xilinx and lattice, respectively).