Closed newinnovations closed 10 months ago
Have a look here: https://github.com/litex-hub/pythondata-cpu-rocket/commit/ef6cf0a11f4a5d384f72b9b3661c85ad81d5e942
The variants have been renamed so on genesys2 you should probably use --cpu-variant linux --cpu-num-cores 4 --cpu-mem-width 4
.
The genesys2 has a 256-bit wide LiteDRAM port, hence --cpu-mem-width 4
. You can pick the --cpu-num-cores
you want, might be able to fit 8 of them on a large FPGA, not exactly sure (but there should be room enough for 4).
NOTE: I'd like to eliminate support for the various --cpu-mem-width
options in the long term, but first I (or someone) would have to fix the LiteX AXI up-converter (https://github.com/enjoy-digital/litex/issues/1753 warning: the comment thread goes a bit off topic :) )
Thanks for the quick reply!
Following the instructions for building for the Digilent Genesys2 ...
... I get the following error:
I am wondering whether I should use
full
orlinux
instead offull4q
? Or maybe I made some error installing litex.Your help is greatly appreciated.