Building error for nexys_video - Unresolved clock domain clk100

Hi,

I tried to build the SW and HW for the Board: Nexys Video. Installed all tools like done in the ci.yml. For the Arty board (--board=arty) which is also using the clk100 pin everything build fine.

When building the nexys_video bitstream directly with litex-boards/litex_boards/targets/nexys_video.py there is no error.

Can you give me some advice, where to search for the cause of the error? The make.py, build tools and dependencies are hard to follow for a beginner.

Here is the log:

~/gits/linux-on-litex-vexriscv$ ./make.py --board=nexys_video --build

INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-03-10 22:58:28)
INFO:SoC:--------------------------------------------------------------------------------

...

chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/rolfes/gits/linux-on-litex-vexriscv/build/nexys_video/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 36.75KiB     (57.42%)
RAM usage: 0.63KiB      (7.91%)

make: Verzeichnis „/home/rolfes/gits/linux-on-litex-vexriscv/build/nexys_video/software/bios“ wird verlassen
Traceback (most recent call last):
  File "/home/rolfes/litex/litex/gen/fhdl/verilog.py", line 394, in convert
    f.clock_domains[cd_name]
  File "/home/rolfes/migen/migen/fhdl/structure.py", line 741, in __getitem__
    raise KeyError(key)
KeyError: 'clk100'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "./make.py", line 634, in <module>
    main()
  File "./make.py", line 615, in main
    builder.build(run=args.build)
  File "/home/rolfes/litex/litex/soc/integration/builder.py", line 217, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/rolfes/litex/litex/soc/integration/soc.py", line 1076, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/rolfes/litex/litex/build/xilinx/platform.py", line 53, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/rolfes/litex/litex/build/xilinx/vivado.py", line 333, in build
    v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/home/rolfes/litex/litex/build/xilinx/platform.py", line 47, in get_verilog
    attr_translate=self.toolchain.attr_translate, **kwargs)
  File "/home/rolfes/litex/litex/build/generic_platform.py", line 413, in get_verilog
    create_clock_domains=False, **kwargs)
  File "/home/rolfes/litex/litex/gen/fhdl/verilog.py", line 404, in convert
    raise Exception(msg)
Exception: Unresolved clock domain clk100, availables:
- sys
- sys4x
- sys4x_dqs
- idelay
- hdmi
- hdmi5x
- pix
- pix5x

litex-hub / linux-on-litex-vexriscv

Building error for nexys_video - Unresolved clock domain clk100 #210