Closed geertu closed 3 years ago
The sample overlay source files can be found at https://gist.github.com/geertu/2ef351008bd614e28b1be20fa1c7361d https://gist.github.com/geertu/59570a10e2a975e5ead5dc14bcc4aa5b
As a picture says more than 1000 words https://society.oftrolls.com/@geert/105996716422075863
FYI -- @shenki @gregdavill @antonblanchard -- I think you'll be interested in both this CL and the picture that @geertu just posted.
@mateusz-holenko / @gsomlo - Do you understand device tree enough to check this looks good?
Thanks @geertu, sorry for the delay. This is a very interesting feature, thanks for sharing your device tree knowledge with us.
FPGA development boards typically have many expansion connectors, while the board DTS as generated by LiteX describes only a part of the system.
Add support for describing hardware connected to expansion connectors using Flattened Device Tree Overlays.
Generation of the final DTB is done in two steps:
Example:
Signed-off-by: Geert Uytterhoeven geert@linux-m68k.org