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Linux on LiteX-VexRiscv
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Linux fails to boot on Orangecrab (85F) with cpu-count=2 #254

Closed essele closed 2 years ago

essele commented 2 years ago

I've got a new 85F Orangecrab and have got it booting nicely with a single core, but when I try cpu-count=2 it doesn't get past the "==== Liftoff! ====" message, which I presume is the opensbi bit.

I have already set l2_size to 0 as per some of the discussions in other logged issues, and that got the bios running ok.

Any ideas, or anywhere I can look for problems?

Dolu1990 commented 2 years ago

Hi,

Are the synthesis timings ok ?

essele commented 2 years ago

Yes, I think so ....

Info: Max frequency for clock '$glbnet$sys_clk': 68.96 MHz (PASS at 64.00 MHz) Info: Max frequency for clock '$glbnet$main_crg_ecp5pll1_clkout1': 95.79 MHz (PASS at 12.00 MHz) Info: Max frequency for clock '$glbnet$clk48$TRELLIS_IO_IN': 309.02 MHz (PASS at 48.00 MHz) Info: Max frequency for clock '$glbnet$main_crg_ecp5pll1_clkout0': 230.57 MHz (PASS at 48.00 MHz) Info: Max frequency for clock '$glbnet$init_clk': 281.37 MHz (PASS at 24.00 MHz)

Dolu1990 commented 2 years ago

Hmmm, and is it booting with the same arguements but in the simulation ?

What exact command line + arguements are you using ?

essele commented 2 years ago

So the sim.py and make.py do wildly different things in terms of what hardware is included, so I'm not sure how that's a fair comparison, am I missing some other way of simulating?

My make.py command line: ./make.py --board orangecrab --device 85F --cpu-count 2 --build (and I have edited make.py to alter l2_size to 0)

If I run ./sim.py --cpu-count 2 it works fine.

essele commented 2 years ago

Further info ... interestingly I get the same behaviour single cpu if l2_size is 0. So with l2_size=0 neither single or dual core will boot .. both stop at "==== Liftoff ====".

With l2_size=2k then the single core one is fine, but the dual-core one doesn't even load the bios (no output at all.)

Dolu1990 commented 2 years ago

that's weird, because the CPU netlists were not updated since a while (+6 months) : https://github.com/litex-hub/pythondata-cpu-vexriscv_smp/tree/master/pythondata_cpu_vexriscv_smp/verilog

So it maybe something broken more recently in the SoC itself ?

enjoy-digital commented 2 years ago

The OrangeCrab has DM pins swapped and with VexRiscv-SMP/Native LiteDRAM interfaces, this need to be fixed in the gateware (since VexRiscv-SMP do partial writes on the DRAM which is not the case when using the L2). I just reverted this in: https://github.com/litex-hub/litex-boards/commit/eb8657f515fe63ced13c487f7da537451d89d993

@essele; Could you do a test with up to date LiteX repos and with 1 then 2 CPUs? (I just tested with 1 CPU here, but only have a 25F, so can't test with 2).

enjoy-digital commented 2 years ago

@essele: I just tested a very similar configuration on the ECPIX5: 2 CPUs with similar FPGA/DDR3. The initial issues you had were:

So things should now be working on the OrangeCrab too.

One thing that still need to be investigated is the behavior with --with-wishbone-memory and --cpu-count > 1 but I'll investigate this separately (and this is not a common use-case).