Board u420t Kintex-t added

[sysmanalex]

Board u420t Kintex-t added

[enjoy-digital]

Thanks @sysmanalex. This board has a big FPGA but does not seem to have DRAM and if so, can't run Linux-on-LiteX-Vexriscv project. Am I missing something?

[sysmanalex]

Big FPGA also contains 34Mb of BRAM, for 417K Luts. https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable The 7 Series FPGAs Memory Resources User Guide (UG473) provides additional details on the block RAM and FIFOs / RAMB18E1 / RAMB38E1 blocks. http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf more here to read here https://support.xilinx.com/s/article/46513?language=en_US

btw check header I did small trick adding BRAM as rom/ram at once, this allow to simple pass demo and other dependencies

• I also used SDRAM from nano-de0 with this board, possibly will design some add-on board for own use.

[enjoy-digital]

Thanks. Regarding the way you enforced integrated_rom/ram/main_ram, I have a preference to avoid it, use the defaults and just let user use command line arguments to enforce sizes. This is preference in LiteX-Boards to simplify maintenance and avoid too much specificities on boards but it's possible to enforce them in your out-of-tree board support.

Even if this FPGA has lots of BRAM, I don't think Vivado will manage to combine in a 32MB RAM without blowing up (Maybe on Ultrascale with UltraRAM), so this would need to be tested.

[sysmanalex]

1st you lead maintainer, decision is on your side. Leaving as comment inside can be also good option 2nd documentation should be improved, for ppls you less know how it works.

Btw same as litex-setup.py There is no clean description for config include/excluding options for

--config=(minimal, standard, full)

I highly recommend to add anotation for them

On Thu, Apr 21, 2022, 08:50 enjoy-digital @.***> wrote:

Thanks. Regarding the way you enforced integrated_rom/ram/main_ram, I have a preference to avoid it, use the defaults and just let user use command line arguments to enforce. This is preference in LiteX-Boards to simplify maintenance and avoid too much specificities on boards but it's possible to enforce them in your out-of-tree board support.

Even if this FPGA has lots of BRAM, I don't think Vivado will manage to combine in a 32MB RAM without blowing up (Maybe on Ultrascale with UltraRAM), so this would need to be tested.

— Reply to this email directly, view it on GitHub https://github.com/litex-hub/linux-on-litex-vexriscv/pull/270#issuecomment-1105167533, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABDBNEIHCXXSQKPQI5UGXATVGFFHLANCNFSM5TISQ6WQ . You are receiving this because you were mentioned.Message ID: @.***>

[enjoy-digital]

Closing since not yet supported/tested. We could integrate if Vivado manage to create large enough RAM.