What's needed in order to add wishbone to axi interface into SoC

[8pins]

I have a project that requires a Linux-compatible SoC to control and stream data from a hardware-implement neural network (NN). The NN uses the AXI bus interface so I need to add a Wishbone2AXI interface to control it. The problem is I'm not sure where and what to add to SoC. Here's what I've understood so far and

• linux-on-litex-vexriscv/make.py will gen the top level SoC with everything included and I can't add or change the bus interface in this make.py
• linux-on-litex-vexriscv/soc_linux.py defines how to add peripherals
• I run SoC on board KC705 so the instance of NN will be added litex-boards/targets/xilinx_kc705.py?
• soc/integration/soc_core.py defines the initial configuration of the SoC so Wishbone2AXI will be added here and then instantiate in xilinx_kc705.py?
• Where and how to add CSR of the NN?
• Do I miss anything? Thank you very much

[enjoy-digital]

Hi Spins,

Linux-on-LiteX-VexRiscv now just basically provides build instructions for Linux and pre-configured SoC targets. To extend it, it could be easier to just generate the SoC from the LiteX-Boards targets (with the same parameters used here) and then customize the SoC as you would do for any LiteX SoC.