litex-hub / linux-on-litex-vexriscv

Linux on LiteX-VexRiscv
BSD 2-Clause "Simplified" License
551 stars 174 forks source link

Arty F4PGA build fails: #300

Open AEW2015 opened 1 year ago

AEW2015 commented 1 year ago

Command: ./make.py --board=arty_a7 --cpu-count=1 --toolchain=symbiflow --build

Error:

Executing module `synthesize`:
    [1/3] : Synthesizing sources: ['/content/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/Ram_1w_1rs_Generic.v', '/content/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw128_Ood.v', '/content/linux-on-litex-vexriscv/build/arty_a7/gateware/arty_a7.v']...
[ERROR]: yosys non-zero return code.
stderr:
ERROR: Cell $iopadmap$arty_a7.sdcard_cd of type \IBUF doesn't support the \SLEW attribute

Removing the SDcard feature, results in error for a missing primitive (likely a F4PGA issue):

[ERROR]: vpr non-zero return code.
stderr:
Error 1: 
Type: Blif file
File: /content/linux-on-litex-vexriscv/build/arty_a7/gateware/arty_a7.eblif
Line: 295055
Message: Failed to find matching architecture model for 'BSCANE2'
mithro commented 1 year ago

@kgugala