litex-hub / linux-on-litex-vexriscv

Linux on LiteX-VexRiscv
BSD 2-Clause "Simplified" License
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OrangeCrab 85F needs --alt 0 for DFU #305

Open edwintorok opened 1 year ago

edwintorok commented 1 year ago

See https://github.com/orangecrab-fpga/orangecrab-hardware/issues/48#issuecomment-1005321004

Also when using the 85F variant then --device=85F has to be added to ./make.py invocations (I was actually able to boot an SMP VexRiscV on this device with ./make.py --board=orangecrab --cpu-count=4 --build --device 85F --icache-size=4096 --icache-ways=1 --dcache-size=4096 --dcache-ways=1 --with-fpu).

E.g.

 class OrangeCrab(Board):
-    soc_kwargs = {"sys_clk_freq" : int(64e6) } # Increase sys_clk_freq to 64MHz (48MHz default).
+    soc_kwargs = {
+        "sys_clk_freq" : int(64e6) ,
+        "max_sdram_size": 0x8000000 # 128 MiB
+    } # Increase sys_clk_freq to 64MHz (48MHz default).
     def __init__(self):
         from litex_boards.targets import gsd_orangecrab
         Board.__init__(self, gsd_orangecrab.BaseSoC, soc_capabilities={
@@ -442,6 +445,8 @@ class OrangeCrab(Board):
             # Storage
             "sdcard",
         })
+    def load(self, filename):
+        os.system("dfu-util --alt 0 --download {} --reset".format(filename))

Not sure whether the dfu changes would be better done elsewhere (e.g. in LiteX itself?) although the same board can have different sized SDRAM on it (so perhaps it should be compiled for the maximum 512MiB?)

enjoy-digital commented 1 year ago

Thanks @edwintorok, I'll see how to best integrate this.