Unable to build for PYNQ Z2

[ratzupaltuff]

I added the Board definition to make.py:

# ZYNQZ2 support -------------------------------------------------------------------------------
class PYNQZ2(Board):
    soc_kwargs = {"uart_name": "serial"}
    def __init__(self):
        from litex_boards.targets import tul_pynq_z2
        Board.__init__(self, tul_pynq_z2.BaseSoC, soc_capabilities={
            # Communication
            "serial"
            "mmcm",
            "icap_bitstream",
        })

But when I compile with: $ ./make.py --board=pynqz2 --toolchain=vivado --build It runs for a while until it says:

...
9 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 3021.000 ; gain = 71.582 ; free physical = 30503 ; free virtual = 37103
# quit
INFO: [Common 17-206] Exiting Vivado at Tue May 16 16:30:04 2023...
Traceback (most recent call last):
  File "/home/tuff/linux-on-litex-vexriscv/./make.py", line 985, in <module>
    main()
  File "/home/tuff/linux-on-litex-vexriscv/./make.py", line 961, in main
    soc.generate_dts(board_name)
  File "/home/tuff/linux-on-litex-vexriscv/soc_linux.py", line 133, in generate_dts
    dts_content = generate_dts(json.load(json_file), polling=False)
  File "/home/tuff/litex/litex/tools/litex_json2dts_linux.py", line 84, in generate_dts
    linux_initrd_start = d["memories"]["main_ram"]["base"] + initrd_start,
KeyError: 'main_ram'

How can I fix this error?

https://github.com/litex-hub/litex-boards/issues/397 This issue looks like its possible to run vexriscv on the Pynq z2. Can someone point me in the right direction?

[trabucayre]

For the mentioned issue: @enjoy-digital's answer is the solution: SoCCore clk_freq is used to have reference frequency to compute some ratio. It's true for the uart baudrate, but since CRG isn't updated PLL's output remains to the default frequency resulting on a wrong baudrate.

For this issue it's an other problem: main_ram region is added when LiteXSoC.add_sdram is called or by using --with-integrated-main-ram-size (default None): for pynq this region isn't added.

You have to keed in mind pynq is based on a zynq (with a CPU and an FPGA). Most of peripherals (uart, ram, sdcard, ethernet) are connected to the PS (CPU) side and not available/managable from FPGA. So you have to add external USB<->uart, sdcard, etc. The most problematic part is related to the RAM: with BRAM I'm not sure you have enough of memory to be able to use Linux.

[ratzupaltuff]

Thank you for the clarification, that helped a lot!