I am trying to replace the LiteDRAM core with MIG, I have a design that already integrates the Xilinx MIG and would like my soc to share the DRAM with that system so that I can read data into my litex soc and process it.
This is what I imagine the architecture should look like.
I am trying to replace the LiteDRAM core with MIG, I have a design that already integrates the Xilinx MIG and would like my soc to share the DRAM with that system so that I can read data into my litex soc and process it.
This is what I imagine the architecture should look like.
From This Post
I made these changes, but I don't think this accounts for the CPU being connected to LiteDRAM, that happens above this.
I also tried to rip out add_sdram and just paste it into my targets file.
Please help me.