Trying to port for TUL PYNQ Z2 Error [KeyError: 'main_ram']

ZeroX29a commented 6 months ago

To the make file I have added this class to support the pynq z2 and updated the supported boards list in the make.py

class pynqz2(Board):
    soc_kwargs = {"uart_name": "serial"}
    def __init__(self):
        from litex_boards.targets import tul_pynq_z2
        Board.__init__(self, tul_pynq_z2.BaseSoC, soc_capabilities={
            "serial",
            # Storage
            "spiflash",
            # GPIOs
            "leds",
            "switches",
            "xadc",
            # 7-Series specific
            "mmcm",
            "icap_bitstream",
        })

and ran the command.
./make.py --board pynqz2 --build Is there anything to be added? please help the error was.

make: Leaving directory '/home/litex/linux-on-litex-vexriscv/build/pynqz2/software/liblitesata'
make: Entering directory '/home/litex/linux-on-litex-vexriscv/build/pynqz2/software/bios'
 CC       boot.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       sim_debug.o
 CC       main.o
 CC       crt0.o
 CC       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.crcfbigen bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/litex/linux-on-litex-vexriscv/build/pynqz2/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 19.28KiB     (30.12%)
RAM usage: 0.05KiB      (0.78%)

rm crt0.o
make: Leaving directory '/home/litex/linux-on-litex-vexriscv/build/pynqz2/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x4d2c).
INFO:SoC:Auto-Resizing ROM rom from 0x10000 to 0x4d2c.
Traceback (most recent call last):
  File "./make.py", line 1012, in <module>
    main()
  File "./make.py", line 988, in main
    soc.generate_dts(board_name)
  File "/home/litex/linux-on-litex-vexriscv/soc_linux.py", line 133, in generate_dts
    dts_content = generate_dts(json.load(json_file), polling=False)
  File "/home/litex/litex_installation/litex/litex/tools/litex_json2dts_linux.py", line 84, in generate_dts
    linux_initrd_start = d["memories"]["main_ram"]["base"] + initrd_start,
KeyError: 'main_ram'

ZeroX29a commented 6 months ago

From the datasheets, DDR is directly connected to PS and not PL so

ZeroX29a commented 6 months ago

i have managed to make it work by adding kwargs["integrated_main_ram_size"] = 0x10000 in /litex_boards/targets/tul_pynq_z2.py

now i get new warning about missing units, can i ignore that?

INFO: [Vivado 12-3199] DRC finished with 0 Errors, 56 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./pynqz2.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.                                            
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 56 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3194.102 ; gain = 46.617 ; free physical = 3274 ; free virtual = 9200
# quit
INFO: [Common 17-206] Exiting Vivado at Sat Dec 30 02:03:31 2023...
build/pynqz2/pynqz2.dts:164.34-175.19: Warning (unit_address_vs_reg): /soc/clk@f0003000/CLKOUT0: node has a reg or ranges property, but no unit name
build/pynqz2/pynqz2.dts:177.34-188.19: Warning (unit_address_vs_reg): /soc/clk@f0003000/CLKOUT1: node has a reg or ranges property, but no unit name

ZeroX29a commented 6 months ago

This turnsout to be a working bitstream but the ram size turned out to be just 6KiB so cant run the linux and increassing the integrated_main_ram_size results in this error

---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2699.109 ; gain = 1076.430 ; free physical = 3341 ; free virtual = 9325
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2699.109 ; gain = 1076.430 ; free physical = 3341 ; free virtual = 9325
---------------------------------------------------------------------------------
WARNING: [Synth 8-3936] Found unconnected internal register 'MmuPlugin_shared_pteBuffer_PPN1_reg' and it is trimmed from '12' to '10' bits. [/home/litex/litex_installation/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ood_Wm_Hb1.v:11670]                                                                            
WARNING: [Synth 8-3936] Found unconnected internal register 'memory_to_writeBack_INSTRUCTION_reg' and it is trimmed from '32' to '30' bits. [/home/litex/litex_installation/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ood_Wm_Hb1.v:8361]                                                                             
WARNING: [Synth 8-3936] Found unconnected internal register 'execute_to_memory_INSTRUCTION_reg' and it is trimmed from '32' to '30' bits. [/home/litex/litex_installation/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ood_Wm_Hb1.v:8142]                                                                               
INFO: [Synth 8-802] inferred FSM for state register 'IBusCachedPlugin_injector_port_state_reg' in module 'VexRiscv'                                                                                   
WARNING: [Synth 8-3936] Found unconnected internal register 'storage_1_dat1_reg' and it is trimmed from '10' to '8' bits. [/home/litex/linux-on-litex-vexriscv/build/pynqz2/gateware/pynqz2.v:2852]   
WARNING: [Synth 8-3936] Found unconnected internal register 'storage_dat1_reg' and it is trimmed from '10' to '8' bits. [/home/litex/linux-on-litex-vexriscv/build/pynqz2/gateware/pynqz2.v:2831]     
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  iSTATE |                              000 |                              000
                 iSTATE0 |                              001 |                              001
                 iSTATE1 |                              010 |                              010
                 iSTATE2 |                              011 |                              011
                 iSTATE3 |                              100 |                              100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'IBusCachedPlugin_injector_port_state_reg' using encoding 'sequential' in module 'VexRiscv'                                                      
WARNING: [Synth 8-6841] Block RAM (main_ram_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.                                                                             
(address width (21) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2699.109 ; gain = 1076.430 ; free physical = 3336 ; free virtual = 9323
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
           2 Input   64 Bit       Adders := 1     
           3 Input   52 Bit       Adders := 1     
           2 Input   33 Bit       Adders := 3     
           3 Input   33 Bit       Adders := 1     
           3 Input   32 Bit       Adders := 2     
           2 Input   32 Bit       Adders := 5     
           2 Input   12 Bit       Adders := 1     
           2 Input    7 Bit       Adders := 2     
           4 Input    7 Bit       Adders := 1     
           2 Input    6 Bit       Adders := 2     
           2 Input    5 Bit       Adders := 2     
           2 Input    4 Bit       Adders := 14    
           3 Input    4 Bit       Adders := 1     
           2 Input    3 Bit       Adders := 1     
           2 Input    2 Bit       Adders := 4     
           2 Input    1 Bit       Adders := 4     
+---XORs : 
           2 Input     32 Bit         XORs := 2     
           2 Input      4 Bit         XORs := 2     
           2 Input      1 Bit         XORs := 6     
+---Registers : 
                       67 Bit    Registers := 1     
                       65 Bit    Registers := 1     
                       64 Bit    Registers := 1     
                       52 Bit    Registers := 1     
                       34 Bit    Registers := 2     
                       33 Bit    Registers := 1     
                       32 Bit    Registers := 89    
                       31 Bit    Registers := 1     
                       30 Bit    Registers := 4     
                       22 Bit    Registers := 3     
                       21 Bit    Registers := 1     
                       16 Bit    Registers := 1     
                       12 Bit    Registers := 4     
                       11 Bit    Registers := 1     
                       10 Bit    Registers := 36    
                        9 Bit    Registers := 1     
                        8 Bit    Registers := 5     
                        7 Bit    Registers := 4     
                        6 Bit    Registers := 16    
                        5 Bit    Registers := 6     
                        4 Bit    Registers := 37    
                        3 Bit    Registers := 9     
                        2 Bit    Registers := 58    
                        1 Bit    Registers := 541   
+---RAMs : 
                   65536K Bit   (2097152 X 32 bit)          RAMs := 1     
                      48K Bit   (1536 X 32 bit)          RAMs := 1     
                      32K Bit   (1024 X 32 bit)          RAMs := 2     
                       1K Bit   (64 X 22 bit)          RAMs := 2     
                      256 Bit   (8 X 32 bit)          RAMs := 1     
                      160 Bit   (16 X 10 bit)          RAMs := 2     
+---ROMs : 
                            ROMs := 1     
+---Muxes : 
           2 Input   64 Bit        Muxes := 5     
           2 Input   34 Bit        Muxes := 1     
           2 Input   33 Bit        Muxes := 3     
           2 Input   32 Bit        Muxes := 158   
           4 Input   32 Bit        Muxes := 11    
           3 Input   32 Bit        Muxes := 4     
          39 Input   32 Bit        Muxes := 1     
           3 Input   30 Bit        Muxes := 1     
           2 Input   16 Bit        Muxes := 1     
           2 Input   14 Bit        Muxes := 2     
           2 Input   12 Bit        Muxes := 1     
           2 Input   10 Bit        Muxes := 11    
           4 Input   10 Bit        Muxes := 4     
           2 Input    8 Bit        Muxes := 17    
           4 Input    8 Bit        Muxes := 1     
           5 Input    8 Bit        Muxes := 1     
           3 Input    8 Bit        Muxes := 2     
           2 Input    7 Bit        Muxes := 2     
           2 Input    6 Bit        Muxes := 15    
           8 Input    6 Bit        Muxes := 1     
           2 Input    5 Bit        Muxes := 13    
           8 Input    5 Bit        Muxes := 2     
           4 Input    5 Bit        Muxes := 2     
           4 Input    4 Bit        Muxes := 3     
           2 Input    4 Bit        Muxes := 23    
           3 Input    4 Bit        Muxes := 1     
           6 Input    4 Bit        Muxes := 1     
           9 Input    4 Bit        Muxes := 2     
           2 Input    3 Bit        Muxes := 10    
           4 Input    3 Bit        Muxes := 1     
           5 Input    3 Bit        Muxes := 4     
           3 Input    3 Bit        Muxes := 1     
           2 Input    2 Bit        Muxes := 85    
           5 Input    2 Bit        Muxes := 1     
           4 Input    2 Bit        Muxes := 1     
           3 Input    2 Bit        Muxes := 5     
           2 Input    1 Bit        Muxes := 585   
           3 Input    1 Bit        Muxes := 23    
           4 Input    1 Bit        Muxes := 19    
           6 Input    1 Bit        Muxes := 1     
           7 Input    1 Bit        Muxes := 2     
           5 Input    1 Bit        Muxes := 6     
          32 Input    1 Bit        Muxes := 124   
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'memory_to_writeBack_MUL_HH_reg' and it is trimmed from '34' to '32' bits. [/home/litex/litex_installation/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ood_Wm_Hb1.v:8125]                                                                                  
WARNING: [Synth 8-3936] Found unconnected internal register 'execute_to_memory_MUL_HH_reg' and it is trimmed from '34' to '32' bits. [/home/litex/litex_installation/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ood_Wm_Hb1.v:8056]                                                                                    
WARNING: [Synth 8-3936] Found unconnected internal register 'MmuPlugin_shared_dBusRspStaged_payload_data_reg' and it is trimmed from '32' to '30' bits. [/home/litex/litex_installation/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ood_Wm_Hb1.v:8944]                                                                 
DSP Report: Generating DSP memory_to_writeBack_MUL_HH_reg, operation Mode is: (A*B)'.
DSP Report: register memory_to_writeBack_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
DSP Report: register execute_to_memory_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
DSP Report: operator execute_MUL_HH is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
DSP Report: Generating DSP execute_to_memory_MUL_LH_reg, operation Mode is: (A*B)'.
DSP Report: register execute_to_memory_MUL_LH_reg is absorbed into DSP execute_to_memory_MUL_LH_reg.
DSP Report: operator execute_MUL_LH is absorbed into DSP execute_to_memory_MUL_LH_reg.
DSP Report: Generating DSP execute_to_memory_MUL_HL_reg, operation Mode is: (A*B)'.
DSP Report: register execute_to_memory_MUL_HL_reg is absorbed into DSP execute_to_memory_MUL_HL_reg.
DSP Report: operator execute_MUL_HL is absorbed into DSP execute_to_memory_MUL_HL_reg.
DSP Report: Generating DSP execute_to_memory_MUL_LL_reg, operation Mode is: (A*B)'.
DSP Report: register execute_to_memory_MUL_LL_reg is absorbed into DSP execute_to_memory_MUL_LL_reg.
DSP Report: operator execute_MUL_LL is absorbed into DSP execute_to_memory_MUL_LL_reg.
RAM Pipeline Warning: Read Address Register Found For RAM sram_reg. We will not be able to pipeline it. This may degrade performance. 
RAM Pipeline Warning: Read Address Register Found For RAM sram_reg. We will not be able to pipeline it. This may degrade performance. 
RAM Pipeline Warning: Read Address Register Found For RAM main_ram_reg. We will not be able to pipeline it. This may degrade performance. 
RAM Pipeline Warning: Read Address Register Found For RAM main_ram_reg. We will not be able to pipeline it. This may degrade performance. 
WARNING: [Synth 8-6841] Block RAM (main_ram_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.                                                                             
(address width (21) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
RAM Pipeline Warning: Read Address Register Found For RAM sram_reg. We will not be able to pipeline it. This may degrade performance. 
RAM Pipeline Warning: Read Address Register Found For RAM main_ram_reg. We will not be able to pipeline it. This may degrade performance. 
WARNING: [Synth 8-3332] Sequential element (FDPE_2) is unused and will be removed from module pynqz2.                                                                                                 
WARNING: [Synth 8-3332] Sequential element (FDPE_3) is unused and will be removed from module pynqz2.                                                                                                 
WARNING: [Synth 8-3332] Sequential element (FDPE_4) is unused and will be removed from module pynqz2.                                                                                                 
WARNING: [Synth 8-3332] Sequential element (FDPE_5) is unused and will be removed from module pynqz2.                                                                                                 
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:50 ; elapsed = 00:00:57 . Memory (MB): peak = 2699.109 ; gain = 1076.430 ; free physical = 3289 ; free virtual = 9322
---------------------------------------------------------------------------------
 Sort Area is  memory_to_writeBack_MUL_HH_reg_5 : 0 0 : 2328 2328 : Used 1 time 0
 Sort Area is  execute_to_memory_MUL_HL_reg_2 : 0 0 : 2298 2298 : Used 1 time 0
 Sort Area is  execute_to_memory_MUL_LH_reg_4 : 0 0 : 2298 2298 : Used 1 time 0
 Sort Area is  execute_to_memory_MUL_LL_reg_0 : 0 0 : 1978 1978 : Used 1 time 0
**ERROR: [Synth 8-5834] Design needs 4122 RAMB18 which is more than device capacity of 280**

Report Cell Usage: 
+------+--------------+------+
|      |Cell          |Count |
+------+--------------+------+
|1     |BUF           |   358|
|2     |BUFG          |     3|
|3     |DSP48E1       |     4|
|4     |GATE_2        |   791|
|6     |GATE_2_14_OR  |  2672|
|7     |GATE_2_1_NOR  |   517|
|8     |GATE_2        |  2558|
|10    |GATE_2_6_XOR  |   897|
|11    |GATE_2_7_NAND |  1219|
|12    |GATE_2_8_AND  |  1522|
|13    |GATE_2_9_XNOR |    38|
|14    |ICAPE2        |     1|
|15    |INV           |   539|
|16    |MMCME2_ADV    |     1|
|17    |MUX1          |  2639|
|18    |MUXCY         |    54|
|19    |MUXCY_L       |   680|
|20    |PLLE2_ADV     |     1|
|21    |RAM32M        |    22|
|22    |RAMB18E1      |     2|
|23    |RAMB36E1      |  2060|
|24    |XADC          |     1|
|25    |XORCY         |   606|
|26    |FD            |   442|
|27    |FDC           |    39|
|28    |FDCE          |   360|
|29    |FDE           |  2811|
|30    |FDP           |     8|
|31    |FDPE          |    16|
|32    |FDR           |   265|
|33    |FDRE          |   394|
|34    |FDS           |    16|
|35    |FDSE          |    50|
+------+--------------+------+

Synthesis Optimization Runtime : Time (s): cpu = 00:00:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2699.109 ; gain = 1012.363 ; free physical = 3289 ; free virtual = 9322
INFO: [Common 17-83] Releasing license: Synthesis
85 Infos, 269 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
INFO: [Common 17-206] Exiting Vivado at Sat Dec 30 13:37:18 2023...
Traceback (most recent call last):
  File "./make.py", line 1012, in <module>
    main()
  File "./make.py", line 985, in main
    builder.build(run=args.build, build_name=board_name)
  File "/home/litex/litex_installation/litex/litex/soc/integration/builder.py", line 370, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/litex/litex_installation/litex/litex/soc/integration/soc.py", line 1383, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/litex/litex_installation/litex/litex/build/xilinx/platform.py", line 98, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/litex/litex_installation/litex/litex/build/xilinx/vivado.py", line 141, in build
    return GenericToolchain.build(self, platform, fragment, **kwargs)
  File "/home/litex/litex_installation/litex/litex/build/generic_toolchain.py", line 123, in build
    self.run_script(script)
  File "/home/litex/litex_installation/litex/litex/build/xilinx/vivado.py", line 401, in run_script
    raise OSError("Error occured during Vivado's script execution.")
OSError: Error occured during Vivado's script execution.

ratzupaltuff commented 5 months ago

I can't help here either but I wanted to add a related issue here, maybe it is interesting for you: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/339

ZeroX29a commented 5 months ago

@ratzupaltuff Thank you, it helped, sadly I think atm its not possible to connect the ddr from PS to PL.

litex-hub / linux-on-litex-vexriscv

Trying to port for TUL PYNQ Z2 Error [KeyError: 'main_ram'] #377