Hello. Could someone point me to the right direction when adding support for a new board :)
make.py:
class Colorlight_5a_75e(Board):
def __init__(self):
from litex_boards.targets import colorlight_5a_75x
Board.__init__(self, colorlight_5a_75x.BaseSoC("5a-75e", "6.0"), soc_capabilities={
# Communication
})
Traceback (most recent call last):
File "/home/roby/repos/linux-on-litex-vexriscv/./make.py", line 998, in <module>
main()
File "/home/roby/repos/linux-on-litex-vexriscv/./make.py", line 866, in main
board = supported_boards[board_name]()
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/roby/repos/linux-on-litex-vexriscv/./make.py", line 538, in __init__
Board.__init__(self, colorlight_5a_75x.BaseSoC("5a-75e", "6.0"), soc_capabilities={
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/roby/litex/litex-boards/litex_boards/targets/colorlight_5a_75x.py", line 145, in __init__
with_rst = kwargs["uart_name"] not in ["serial", "crossover"] # serial_rx shared with user_btn_n.
~~~~~~^^^^^^^^^^^^^
KeyError: 'uart_name'
(.venv) [roby@thonkpad linux-on-litex-vexriscv]$
Hello. Could someone point me to the right direction when adding support for a new board :)
make.py
:./make.py --board=colorlight_5a_75e --cpu-count=1 --build
: