Ethernet not working on genesys 2

[elialaz]

Hi everyone,

I have a dubs about the regeneration process of the Verilog of the VexRiscV core, in particular I trying to modify the core inside the pythondata-cpu-vexriscv_smp repository and adding a custom plugin inside it, my dubs are about how can I regenerate the Verilog of the core with my custom implementation inside and then basically run the standard workflow for the bitstream build and load inside this repository.

Just for reference in my case I modified the standard VexRiscvSmpClusterGen class to include my plugin so it will be included in the standard config used for the build.

Any clarification should be helpfully Thanks a lot

[elialaz]

For everyone I manage to find how to regenerate, just run the generate.py script inside the pythondata-cpu-vexriscv-smp

I think should be useful to add this to the README under the link to the sdb

Now i have a new problem, basically the eth0 interface on the genesys 2 board doesn't work (besides my custom Core)

Here the log:

--============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro [LITEX-TERM] Received firmware download request from the device. [LITEX-TERM] Uploading images/Image to 0x40000000 (7531468 bytes)... [LITEX-TERM] Upload calibration... (inter-frame: 10.00us, length: 64) [LITEX-TERM] Upload complete (82.3KB/s). [LITEX-TERM] Uploading images/rv32.dtb to 0x40ef0000 (3083 bytes)... [LITEX-TERM] Upload calibration... (inter-frame: 10.00us, length: 64) [LITEX-TERM] Upload complete (67.2KB/s). [LITEX-TERM] Uploading images/rootfs.cpio to 0x41000000 (3781632 bytes)... [LITEX-TERM] Upload calibration... (inter-frame: 10.00us, length: 64) [LITEX-TERM] Upload complete (81.5KB/s). [LITEX-TERM] Uploading images/opensbi.bin to 0x40f00000 (53640 bytes)... [LITEX-TERM] Upload calibration... (inter-frame: 10.00us, length: 64) [LITEX-TERM] Upload complete (70.0KB/s). [LITEX-TERM] Booting the device. [LITEX-TERM] Done. Executing booted program at 0x40f00000

--============= Liftoff! ===============--

OpenSBI v0.8-1-gecf7701

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Platform Name : LiteX / VexRiscv-SMP Platform Features : timer,mfdeleg Platform HART Count : 8 Boot HART ID : 0 Boot HART ISA : rv32imasu BOOT HART Features : pmp,scounteren,mcounteren,time BOOT HART PMP Count : 16 Firmware Base : 0x40f00000 Firmware Size : 124 KB Runtime SBI Version : 0.2

MIDELEG : 0x00000222 MEDELEG : 0x0000b109 [ 0.000000] Linux version 5.14.0 (florent@panda) (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2021.08-381-g279167ee8d) 10.3.0, GNU ld (GNU Binutils) 2.36.1) #1 SMP Tue Sep 21 12:57:31 CEST 2021 [ 0.000000] earlycon: liteuart0 at I/O port 0x0 (options '') [ 0.000000] Malformed early option 'console' [ 0.000000] earlycon: liteuart0 at MMIO 0xf0001000 (options '') [ 0.000000] printk: bootconsole [liteuart0] enabled [ 0.000000] Zone ranges: [ 0.000000] Normal [mem 0x0000000040000000-0x000000007fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff] [ 0.000000] SBI specification v0.2 detected [ 0.000000] SBI implementation ID=0x1 Version=0x8 [ 0.000000] SBI TIME extension detected [ 0.000000] SBI IPI extension detected [ 0.000000] SBI RFENCE extension detected [ 0.000000] SBI v0.2 HSM extension detected [ 0.000000] riscv: ISA extensions aimp [ 0.000000] riscv: ELF capabilities aim [ 0.000000] percpu: Embedded 8 pages/cpu s11340 r0 d21428 u32768 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [ 0.000000] Kernel command line: console=liteuart earlycon=liteuart,0xf0001000 rootwait root=/dev/ram0 ip=192.168.1.50:192.168.1.100:192.168.1.100:255.255.255.0::eth0:off::: [ 0.000000] Unknown command line parameters: ip=192.168.1.50:192.168.1.100:192.168.1.100:255.255.255.0::eth0:off::: [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear) [ 0.000000] Sorting __ex_table... [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] Memory: 1023284K/1048576K available (5685K kernel code, 572K rwdata, 883K rodata, 209K init, 221K bss, 25292K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [ 0.000000] rcu: Hierarchical RCU implementation. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] riscv-intc: 32 local interrupts mapped [ 0.000000] plic: interrupt-controller@f0c00000: mapped 32 interrupts with 1 handlers for 2 contexts. [ 0.000000] random: get_random_bytes called from start_kernel+0x4ac/0x63c with crng_init=0 [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns [ 0.000019] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns [ 0.002370] Console: colour dummy device 80x25 [ 0.003397] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) [ 0.005023] pid_max: default: 32768 minimum: 301 [ 0.009093] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear) [ 0.010489] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear) [ 0.033473] ASID allocator using 9 bits (512 entries) [ 0.036375] rcu: Hierarchical SRCU implementation. [ 0.042497] smp: Bringing up secondary CPUs ... [ 0.043121] smp: Brought up 1 node, 1 CPU [ 0.049701] devtmpfs: initialized [ 0.082281] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.083724] futex hash table entries: 256 (order: 2, 16384 bytes, linear) [ 0.092303] NET: Registered PF_NETLINK/PF_ROUTE protocol family [ 0.281406] pps_core: LinuxPPS API ver. 1 registered [ 0.282292] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti giometti@linux.it [ 0.283567] PTP clock support registered [ 0.287569] FPGA manager framework [ 0.302238] clocksource: Switched to clocksource riscv_clocksource [ 0.473297] NET: Registered PF_INET protocol family [ 0.475988] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear) [ 0.496861] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) [ 0.498743] TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear) [ 0.500790] TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.503465] TCP: Hash tables configured (established 8192 bind 8192) [ 0.505145] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) [ 0.506745] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) [ 0.526836] Unpacking initramfs... [ 0.582514] workingset: timestamp_bits=30 max_order=18 bucket_order=0 [ 0.819127] io scheduler mq-deadline registered [ 0.819781] io scheduler kyber registered [ 1.113526] LiteX SoC Controller driver initialized [ 2.041599] Initramfs unpacking failed: invalid magic at start of compressed archive [ 2.105210] Freeing initrd memory: 8192K [ 2.704530] f0001000.serial: ttyLXU0 at MMIO 0x0 (irq = 0, base_baud = 0) is a liteuart [ 2.706220] printk: console [liteuart0] enabled [ 2.706220] printk: console [liteuart0] enabled [ 2.706945] printk: bootconsole [liteuart0] disabled [ 2.706945] printk: bootconsole [liteuart0] disabled [ 2.740966] liteeth f0002000.mac eth0: irq 2 slots: tx 2 rx 2 size 2048 [ 2.745272] i2c_dev: i2c /dev entries driver [ 2.787230] NET: Registered PF_INET6 protocol family [ 2.803858] Segment Routing with IPv6 [ 2.804811] In-situ OAM (IOAM) with IPv6 [ 2.806764] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver [ 2.820780] NET: Registered PF_PACKET protocol family [ 2.842225] litex-mmc f0006000.mmc: Requested clk_freq=12500000: set to 12500000 via div=8 [ 2.857253] litex-mmc f0006000.mmc: Requested clk_freq=0: set to 390625 via div=256 [ 2.871192] Freeing unused kernel image (initmem) memory: 204K [ 2.872046] Kernel memory protection not selected by kernel config. [ 2.873001] Run /init as init process Starting syslogd: OK Starting klogd: OK Running sysctl: OK Saving random seed: [ 5.204552] random: dd: uninitialized urandom read (512 bytes read) OK Starting network: OK

Welcome to Buildroot buildroot login: root

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              / /  (_)__  __ ____ __
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_ _ \//// / / () /____ | |//| | / /__ / () ___ / // / / -_)> </__/ |/ / -) \ // , / (-</ / |/ / /_//_/_//||___|/_/_\//|/_//_/|_/ / / |/ / \ \ \/ /|/ / / /__// /// 32-bit RISC-V Linux running on LiteX / VexRiscv-SMP.

login[71]: root login on 'console' root@buildroot:~# ifconfig -a eth0 Link encap:Ethernet HWaddr 7A:D8:7B:4F:01:55 BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:2

lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

sit0 Link encap:IPv6-in-IPv4 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

root@buildroot:~# ifconfig -a eth0 Link encap:Ethernet HWaddr 7A:D8:7B:4F:01:55 BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:2

lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

sit0 Link encap:IPv6-in-IPv4 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

root@buildroot:~# ifdown eth0 ifdown: interface eth0 not configured root@buildroot:~# ifup eth0 ifup: ignoring unknown interface eth0 root@buildroot:~#

I think is something related to the interrupts on the interface

[Dolu1990]

Hi,

just run the generate.py script inside the pythondata-cpu-vexriscv-smp

the pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster.v files are just there as pregenerated. If you ask a config which isn't generated, then litex will run the SpinalHDL generation. So, in other words, if you tweek the VexRiscv core and want litex to use the updated design, you just need to delete all the VexRiscvLitexSmpCluster.v files.

Ethernet not working

It may be related to a DTS/DTB missmatch ? Did you used the DTS/DTB generated by litex ? or used some from other devboard ?

[elialaz]

Hi @Dolu1990,

Firstly thanks to the reply, I modified the config from witch the pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster*.v files are generated for simplicity and a more plug and play approach.

For the Ethernet I tried both the litex generated one and another one made by me but I constantly obtaining the interrupt on the interface that makes the OS do not recognize it. If you have suggestions I could try it but anyway I will make some test in the next days.

Another thing, I managed to generate a buildroot configuration with an integrated cpp compiler to easily test programs inside Linux, I found another issue regarding the update of the addressed in the .json file but I cannot manage to make it work by uploading directly with UART so I m trying to load the image on the sd card and boot from them, is the “standard” procedure or I need to make some adjustments to make it work?

Thanks in advance

[Dolu1990]

If you have suggestions

So far i got ethernet to work fine on Arty A7 and Digilent Nexys Video. In buildroot i had to run the command : udhcpc -i eth0 in order to get it up.

found another issue regarding the update of the addressed in the .json file

What is it ?

is the “standard” procedure or I need to make some adjustments to make it work?

So, when i debug with small images, i'm often directly loading stuff via JTAG (~800 KB/s) Else i'm using sdcard or the ethernet interface directly. I'm kinda never using the uart interface, as it is very slow.

[elialaz]

Hi @Dolu1990, seems that I was having an issue on my side on my pc, now I resolved everything. Thanks for the advices!

Can I ask you a question, running some c exec in the linux buildroot seems that the csr register access are restricted for every register, you added some extra configuration parameters for this?

I need to disable this protection to be able to access some basic register like cycle and so on.

[Dolu1990]

In user mode, you should normaly have access to rdcycle and instret.

is it working ?

[elialaz]

@Dolu1990 No but I found out why, by default the fullCsr variable is false so the register are initialized with CsrAccess.NONE I just changed it and then they are accessible

[Dolu1990]

Ahhh right, i understood the question in reverse, sorry XD

[elialaz]

@Dolu1990 do not worry :)

In the next month when I will be more free I will fork (and then ask for a merge) the repository to add more stuff in the documentation, small things that are already mentioned in resolved issues and so on that maybe will help future users speed up their processes.

[Dolu1990]

Thanks :D