Dolu1990
commented
3 days ago Fixed :)
Open GMXX opened 3 days ago
Dolu1990
commented
3 days ago Fixed :)
GMXX
commented
2 days ago Hi, @Dolu1990
I've just tested it again on a clean, from-scratch install, and the problem persists, i.e., it is still trying to create the SoC rather than using the pre-generated. I double-checked, and both the commits were added, as expected.
Can you take a further look, please?
Dolu1990
commented
1 day ago When you run sim.py, you still get :
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------And nothing else ? No idea were Litex is stuck / waiting ?
GMXX
commented
15 hours ago Yes, I still get it. Here is the full output of sim.py:
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-09-26 13:34:02)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv_smp added.
INFO:SoC:CPU vexriscv_smp adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv_smp overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv_smp setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv_smp adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU vexriscv_smp adding SoC components.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCBusHandler:opensbi Region added at Origin: 0x40f00000, Size: 0x00080000, Mode: RW, Cached: True, Linker: True.
INFO:SoCBusHandler:plic Region added at Origin: 0xf0c00000, Size: 0x00400000, Mode: RW, Cached: False, Linker: False.
INFO:SoCBusHandler:plic added as Bus Slave.
INFO:SoCBusHandler:clint Region added at Origin: 0xf0010000, Size: 0x00010000, Mode: RW, Cached: False, Linker: False.
INFO:SoCBusHandler:clint added as Bus Slave.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00010000, Mode: RX, Cached: True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00010000, Mode: RX, Cached: True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 1.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 2.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x04000000, Mode: RWX, Cached: True, Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False, Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (1 <-> 6).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:sdram CSR allocated at Location 1.
INFO:SoCCSRHandler:supervisor CSR allocated at Location 4.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False, Linker: False
Bus Regions: (7)
rom : Origin: 0x00000000, Size: 0x00010000, Mode: RX, Cached: True, Linker: False
sram : Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True, Linker: False
main_ram : Origin: 0x40000000, Size: 0x04000000, Mode: RWX, Cached: True, Linker: False
opensbi : Origin: 0x40f00000, Size: 0x00080000, Mode: RW, Cached: True, Linker: True
csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False, Linker: False
clint : Origin: 0xf0010000, Size: 0x00010000, Mode: RW, Cached: False, Linker: False
plic : Origin: 0xf0c00000, Size: 0x00400000, Mode: RW, Cached: False, Linker: False
Bus Masters: (1)
- cpu_bus0
Bus Slaves: (6)
- plic
- clint
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (5)
- ctrl : 0
- sdram : 1
- uart : 2
- timer0 : 3
- supervisor : 4
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (3)
- noirq : 0
- uart : 1
- timer0 : 2
INFO:SoC:--------------------------------------------------------------------------------
VexRiscv cluster : VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
SoCLinux
└─── crg (CRG)
└─── bus (SoCBusHandler)
│ └─── _interconnect (InterconnectShared)
│ │ └─── arbiter (Arbiter)
│ │ │ └─── rr (RoundRobin)
│ │ └─── decoder (Decoder)
│ │ └─── timeout (Timeout)
│ │ │ └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (VexRiscvSMP)
│ └─── [VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1]
└─── rom (SRAM)
└─── sram (SRAM)
└─── uart_phy (RS232PHYModel)
└─── uart (UART)
│ └─── ev (EventManager)
│ │ └─── eventsourceprocess_0* (EventSourceProcess)
│ │ └─── eventsourceprocess_1* (EventSourceProcess)
│ └─── tx_fifo (SyncFIFO)
│ │ └─── fifo (SyncFIFOBuffered)
│ │ │ └─── fifo (SyncFIFO)
│ └─── rx_fifo (SyncFIFO)
│ │ └─── fifo (SyncFIFOBuffered)
│ │ │ └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│ └─── ev (EventManager)
│ │ └─── eventsourceprocess_0* (EventSourceProcess)
└─── supervisor (Supervisor)
└─── sdrphy (SDRAMPHYModel)
│ └─── dfiphasemodel_0* (DFIPhaseModel)
│ └─── bankmodel_0* (BankModel)
│ └─── bankmodel_1* (BankModel)
│ └─── bankmodel_2* (BankModel)
│ └─── bankmodel_3* (BankModel)
└─── sdram (LiteDRAMCore)
│ └─── dfii (DFIInjector)
│ │ └─── pi0 (PhaseInjector)
│ └─── controller (LiteDRAMController)
│ │ └─── refresher (Refresher)
│ │ │ └─── timer (RefreshTimer)
│ │ │ └─── postponer (RefreshPostponer)
│ │ │ └─── sequencer (RefreshSequencer)
│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_0* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_1* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_2* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_3* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── multiplexer (Multiplexer)
│ │ │ └─── choose_cmd (_CommandChooser)
│ │ │ │ └─── roundrobin_0* (RoundRobin)
│ │ │ └─── choose_req (_CommandChooser)
│ │ │ │ └─── roundrobin_0* (RoundRobin)
│ │ │ └─── _steerer_0* (_Steerer)
│ │ │ └─── trrdcon (tXXDController)
│ │ │ └─── tfawcon (tFAWController)
│ │ │ └─── tccdcon (tXXDController)
│ │ │ └─── twtrcon (tXXDController)
│ │ │ └─── fsm (FSM)
│ └─── crossbar (LiteDRAMCrossbar)
│ │ └─── roundrobin_0* (RoundRobin)
│ │ └─── roundrobin_1* (RoundRobin)
│ │ └─── roundrobin_2* (RoundRobin)
│ │ └─── roundrobin_3* (RoundRobin)
└─── converter_0* (Converter)
└─── wishbone_bridge (LiteDRAMWishbone2Native)
│ └─── fsm (FSM)
└─── csr_bridge (Wishbone2CSR)
│ └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│ └─── csrbank_0* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ └─── csrbank_1* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstorage_2* (CSRStorage)
│ │ └─── csrstorage_3* (CSRStorage)
│ │ └─── csrstorage_4* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ └─── csrbank_2* (CSRBank)
│ └─── csrbank_3* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstorage_2* (CSRStorage)
│ │ └─── csrstorage_3* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstorage_4* (CSRStorage)
│ └─── csrbank_4* (CSRBank)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstatus_3* (CSRStatus)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstatus_4* (CSRStatus)
│ │ └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.
INFO:SoC:--------------------------------------------------------------------------------
Traceback (most recent call last):
File "/content/linux-on-litex-vexriscv/./sim.py", line 179, in <module>
main()
File "/content/linux-on-litex-vexriscv/./sim.py", line 173, in main
builder.build(sim_config=sim_config, run=run, **verilator_build_kwargs)
File "/content/litex/litex/soc/integration/builder.py", line 393, in build
self._check_meson()
File "/content/litex/litex/soc/integration/builder.py", line 311, in _check_meson
raise OSError(msg)
OSError: Unable to find valid Meson build system, please install it with:
- pip3 install meson.It is complaining about meson, but once I install it, it will complain about everything else needed to build the SoC (ninja, etc.) until it can finally fully build it instead of just booting the pre-generated.
Dolu1990
commented
4 hours ago some regular VexRiscv-smp configurations are already pre-generated
Yes, the verilog of the VexRiscv soc part is pregenerated.
Still it needs to compile the software which will run on it.
Those other dependencies (ninja / meson) are requirements with no pregeneration possibilities.
According to the documentation, some regular VexRiscv-smp configurations are already pre-generated, but when running
sim.py, it starts by creating an SoC instead of booting:The README instructions worked as expected some months ago. How can I get the pre-generated configurations?