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litex-hub / linux-on-litex-vexriscv

Linux on LiteX-VexRiscv
BSD 2-Clause "Simplified" License
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finish ULX3S support #5

Closed enjoy-digital closed 5 years ago

enjoy-digital commented 5 years ago

ULX3S is alsmot booting, but https://github.com/enjoy-digital/linux-on-litex-vexriscv/issues/4 prevents it to go to user space. When programming the board with OpenOCD, the serial is no longer detected and then prevents using lxterm to load the linux images. When loading the ujprog, the serial is still detected correctly after bitstream is loaded.

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|

 (c) Copyright 2012-2019 Enjoy-Digital
 (c) Copyright 2012-2015 M-Labs Ltd

 BIOS built on May  7 2019 09:40:21
 BIOS CRC passed (c64754ab)

--============ SoC info ================--
CPU:       VexRiscv @ 50MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  32768KB

--========= Peripherals init ===========--
Initializing SDRAM...
SDRAM now under hardware control
Memtest OK

--========== Boot sequence =============--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading binaries/Image to 0xc0000000 (2726132 bytes)...
[LXTERM] Upload complete (15.3KB/s).
[LXTERM] Uploading binaries/rootfs.cpio to 0xc0800000 (4054528 bytes)...
[LXTERM] Upload complete (15.3KB/s).
[LXTERM] Uploading binaries/rv32.dtb to 0xc1000000 (1618 bytes)...
[LXTERM] Upload complete (14.1KB/s).
[LXTERM] Uploading emulator/emulator.bin to 0x20000000 (9128 bytes)...
[LXTERM] Upload complete (15.0KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x20000000
--============= Liftoff! ===============--
VexRiscv Machine Mode software built May  7 2019 10:01:09
--========== Booting Linux =============--
[    0.000000] No DTB passed to the kernel
[    0.000000] Linux version 5.0.9 (florent@lab) (gcc version 8.3.0 (Buildroot 2019.05-git-00938-g75f9fcd0c9)) #1 Thu May 2 17:43:30 CEST 2019
[    0.000000] Initial ramdisk at: 0x(ptrval) (8388608 bytes)
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x00000000c0000000-0x00000000c7ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x00000000c0000000-0x00000000c7ffffff]
[    0.000000] Initmem setup node 0 [mem 0x00000000c0000000-0x00000000c7ffffff]
[    0.000000] elf_hwcap is 0x1100
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32512
[    0.000000] Kernel command line: mem=32M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Sorting __ex_table...
[    0.000000] Memory: 119052K/131072K available (1957K kernel code, 92K rwdata, 317K rodata, 104K init, 184K bss, 12020K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x114c1bade8, max_idle_ns: 440795203839 ns
[    0.000699] sched_clock: 64 bits at 75MHz, resolution 13ns, wraps every 2199023255546ns
[    0.005987] Console: colour dummy device 80x25
[    0.026123] printk: console [hvc0] enabled
[    0.030423] Calibrating delay loop (skipped), value calculated using timer frequency.. 150.00 BogoMIPS (lpj=300000)
[    0.032373] pid_max: default: 32768 minimum: 301
[    0.067479] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.069751] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.266660] devtmpfs: initialized
[    0.424107] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.426071] futex hash table entries: 256 (order: -1, 3072 bytes)
[    0.964934] clocksource: Switched to clocksource riscv_clocksource
[    2.118148] Unpacking initramfs...
[    8.935616] Initramfs unpacking failed: junk in compressed archive
[    9.015373] workingset: timestamp_bits=30 max_order=15 bucket_order=0
[   10.362975] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
[   10.364303] io scheduler mq-deadline registered
[   10.365359] io scheduler kyber registered
[   17.700662] random: get_random_bytes called from init_oops_id+0x4c/0x60 with crng_init=0
[   42.084334] OF: fdt: not creating '/sys/firmware/fdt': CRC check failed
[   42.144834] Freeing unused kernel memory: 104K
[   42.147410] This architecture does not have kernel memory protection.
[   42.148354] Run /init as init process
enjoy-digital commented 5 years ago

With #4 fixed, it's now booting correctly:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|

 (c) Copyright 2012-2019 Enjoy-Digital
 (c) Copyright 2012-2015 M-Labs Ltd

 BIOS built on May  7 2019 11:34:11
 BIOS CRC passed (94cbc412)

--============ SoC info ================--
CPU:       VexRiscv @ 50MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  32768KB

--========= Peripherals init ===========--
Initializing SDRAM...
SDRAM now under hardware control
Memtest OK

--========== Boot sequence =============--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading binaries/Image to 0xc0000000 (2726132 bytes)...
[LXTERM] Upload complete (15.3KB/s).
[LXTERM] Uploading binaries/rootfs.cpio to 0xc0800000 (4054528 bytes)...
[LXTERM] Upload complete (15.3KB/s).
[LXTERM] Uploading binaries/rv32.dtb to 0xc1000000 (1866 bytes)...
[LXTERM] Upload complete (14.2KB/s).
[LXTERM] Uploading emulator/emulator.bin to 0x20000000 (9128 bytes)...
[LXTERM] Upload complete (15.1KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x20000000
--============= Liftoff! ===============--
VexRiscv Machine Mode software built May  7 2019 11:15:54
--========== Booting Linux =============--
[    0.000000] No DTB passed to the kernel
[    0.000000] Linux version 5.0.9 (florent@lab) (gcc version 8.3.0 (Buildroot 2019.05-git-00938-g75f9fcd0c9)) #1 Thu May 2 17:43:30 CEST 2019
[    0.000000] Initial ramdisk at: 0x(ptrval) (8388608 bytes)
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x00000000c0000000-0x00000000c1ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x00000000c0000000-0x00000000c1ffffff]
[    0.000000] Initmem setup node 0 [mem 0x00000000c0000000-0x00000000c1ffffff]
[    0.000000] elf_hwcap is 0x1101
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 8128
[    0.000000] Kernel command line: mem=32M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32
[    0.000000] Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Sorting __ex_table...
[    0.000000] Memory: 21588K/32768K available (1957K kernel code, 92K rwdata, 317K rodata, 104K init, 184K bss, 11180K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x114c1bade8, max_idle_ns: 440795203839 ns
[    0.000694] sched_clock: 64 bits at 75MHz, resolution 13ns, wraps every 2199023255546ns
[    0.006007] Console: colour dummy device 80x25
[    0.026125] printk: console [hvc0] enabled
[    0.030447] Calibrating delay loop (skipped), value calculated using timer frequency.. 150.00 BogoMIPS (lpj=300000)
[    0.032399] pid_max: default: 32768 minimum: 301
[    0.068752] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.073240] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.269172] devtmpfs: initialized
[    0.436467] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.438471] futex hash table entries: 256 (order: -1, 3072 bytes)
[    1.002666] clocksource: Switched to clocksource riscv_clocksource
[    2.151693] Unpacking initramfs...
[    9.037214] Initramfs unpacking failed: junk in compressed archive
[    9.117003] workingset: timestamp_bits=30 max_order=13 bucket_order=0
[   10.469731] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
[   10.471119] io scheduler mq-deadline registered
[   10.472172] io scheduler kyber registered
[   17.818164] random: get_random_bytes called from init_oops_id+0x4c/0x60 with crng_init=0
[   17.942082] Freeing unused kernel memory: 104K
[   17.944665] This architecture does not have kernel memory protection.
[   17.945622] Run /init as init process
mount: mounting tmpfs on /dev/shm failed: Invalid argument
mount: mounting tmpfs on /tmp failed: Invalid argument
mount: mounting tmpfs on /run failed: Invalid argument
Starting syslogd: OK
Starting klogd: OK
Initializing random number generator... [   27.893920] random: dd: uninitialized urandom read (512 bytes read)
done.
Starting network: ip: socket: Function not implemented
ip: socket: Function not implemented
FAIL

Welcome to Buildroot
buildroot login: root
login[48]: root login on 'hvc0'
kamejoko80 commented 5 years ago

I got an error when building ulx3s

ERROR: Max frequency for clock '$glbnet$main_soclinux_clkout0': 45.65 MHz (FAIL at 50.00 MHz)

Info: Max delay -> posedge $glbnet$main_soclinux_clkout0: 4.53 ns Info: Max delay posedge $glbnet$main_soclinux_clkout0 -> : 4.24 ns

Is there any problem with the synthesizer tool nextpnr-ecp5?

Full log message is below:

./make.py --board=ulx3s --build

/home/phuong/Workspace/Projects/LITEX/linux-on-litex-vexriscv/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:898: Warning: System task `$display' outside initial block is unsupported. Warning: Conflicting init values for signal \main_soclinux_sdram_trrdcon_ready (\main_soclinux_sdram_trrdcon_ready = 1'1, \main_soclinux_sdram_choose_req_want_activates = 1'0). Warning: Wire top.builder_array_muxed0 has an unprocessed 'init' attribute. Warning: Wire top.builder_array_muxed1 has an unprocessed 'init' attribute. Warning: Wire top.builder_array_muxed5 has an unprocessed 'init' attribute. Warning: Wire top.builder_array_muxed6 has an unprocessed 'init' attribute. Warning: Wire top.builder_bankmachine0_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_bankmachine1_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_bankmachine2_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_bankmachine3_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_cache_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_litedramwishbone2native_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_multiplexer_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_refresher_next_state has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed12 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed13 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed15 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed16 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed18 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed19 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed21 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed22 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed24 has an unprocessed 'init' attribute. Warning: Wire top.builder_rhs_array_muxed32 has an unprocessed 'init' attribute. Warning: Wire top.builder_soclinux_error has an unprocessed 'init' attribute. Warning: Wire top.builder_soclinux_slave_sel has an unprocessed 'init' attribute. Warning: Wire top.main_emulator_ram_we has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_cache_data_port_dat_w has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_cache_data_port_we has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_cache_tag_di_dirty has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_cache_tag_port_we has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_port_cmd_payload_addr has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_port_cmd_payload_we has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_choose_req_want_activates has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_inti_p0_rddata has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_inti_p0_rddata_valid has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_address has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_bank has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_cas_n has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_cke has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_cs_n has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_ras_n has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_rddata_en has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_we_n has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_wrdata has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_master_p0_wrdata_en has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sdram_trrdcon_ready has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_sram_we has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_uart_eventmanager_status_w has an unprocessed 'init' attribute. Warning: Wire top.main_soclinux_vexriscv_interrupt0 has an unprocessed 'init' attribute. Info: Importing module top Info: Rule checker, verifying imported design Info: Checksum: 0x02a4b064

Info: constraining clock net 'clk25' to 25.00 MHz Info: constraining clock net 'clk25' to 25.00 MHz

Info: Packing IOs.. Info: pin 'wifi_gpio0$tr_io' constrained to Bel 'X0/Y62/PIOD'. Info: pin 'serial_tx$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'serial_rx$tr_io' constrained to Bel 'X0/Y65/PIOB'. Info: pin 'clk25$tr_io' constrained to Bel 'X0/Y35/PIOA'. Info: pin 'rst$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 'sdram_clock$tr_io' constrained to Bel 'X90/Y26/PIOB'. Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X90/Y35/PIOB'. Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X90/Y35/PIOD'. Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X90/Y35/PIOA'. Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X90/Y35/PIOC'. Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X90/Y32/PIOD'. Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X90/Y32/PIOB'. Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X90/Y29/PIOD'. Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X90/Y32/PIOC'. Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X90/Y32/PIOA'. Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X90/Y29/PIOB'. Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X90/Y59/PIOA'. Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X90/Y26/PIOD'. Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X90/Y29/PIOA'. Info: sdram_dq[0] feeds TRELLIS_IO TRELLIS_IO, removing $nextpnr_ibuf sdram_dq[0]. Info: pin 'TRELLIS_IO' constrained to Bel 'X90/Y20/PIOD'. Info: sdram_dq[1] feeds TRELLIS_IO TRELLIS_IO_1, removing $nextpnr_ibuf sdram_dq[1]. Info: pin 'TRELLIS_IO_1' constrained to Bel 'X90/Y38/PIOC'. Info: sdram_dq[2] feeds TRELLIS_IO TRELLIS_IO_2, removing $nextpnr_ibuf sdram_dq[2]. Info: pin 'TRELLIS_IO_2' constrained to Bel 'X90/Y38/PIOD'. Info: sdram_dq[3] feeds TRELLIS_IO TRELLIS_IO_3, removing $nextpnr_ibuf sdram_dq[3]. Info: pin 'TRELLIS_IO_3' constrained to Bel 'X90/Y41/PIOC'. Info: sdram_dq[4] feeds TRELLIS_IO TRELLIS_IO_4, removing $nextpnr_ibuf sdram_dq[4]. Info: pin 'TRELLIS_IO_4' constrained to Bel 'X90/Y59/PIOD'. Info: sdram_dq[5] feeds TRELLIS_IO TRELLIS_IO_5, removing $nextpnr_ibuf sdram_dq[5]. Info: pin 'TRELLIS_IO_5' constrained to Bel 'X90/Y65/PIOD'. Info: sdram_dq[6] feeds TRELLIS_IO TRELLIS_IO_6, removing $nextpnr_ibuf sdram_dq[6]. Info: pin 'TRELLIS_IO_6' constrained to Bel 'X90/Y68/PIOD'. Info: sdram_dq[7] feeds TRELLIS_IO TRELLIS_IO_7, removing $nextpnr_ibuf sdram_dq[7]. Info: pin 'TRELLIS_IO_7' constrained to Bel 'X90/Y62/PIOD'. Info: sdram_dq[8] feeds TRELLIS_IO TRELLIS_IO_8, removing $nextpnr_ibuf sdram_dq[8]. Info: pin 'TRELLIS_IO_8' constrained to Bel 'X90/Y23/PIOD'. Info: sdram_dq[9] feeds TRELLIS_IO TRELLIS_IO_9, removing $nextpnr_ibuf sdram_dq[9]. Info: pin 'TRELLIS_IO_9' constrained to Bel 'X90/Y23/PIOC'. Info: sdram_dq[10] feeds TRELLIS_IO TRELLIS_IO_10, removing $nextpnr_ibuf sdram_dq[10]. Info: pin 'TRELLIS_IO_10' constrained to Bel 'X90/Y23/PIOB'. Info: sdram_dq[11] feeds TRELLIS_IO TRELLIS_IO_11, removing $nextpnr_ibuf sdram_dq[11]. Info: pin 'TRELLIS_IO_11' constrained to Bel 'X90/Y23/PIOA'. Info: sdram_dq[12] feeds TRELLIS_IO TRELLIS_IO_12, removing $nextpnr_ibuf sdram_dq[12]. Info: pin 'TRELLIS_IO_12' constrained to Bel 'X90/Y14/PIOC'. Info: sdram_dq[13] feeds TRELLIS_IO TRELLIS_IO_13, removing $nextpnr_ibuf sdram_dq[13]. Info: pin 'TRELLIS_IO_13' constrained to Bel 'X90/Y14/PIOD'. Info: sdram_dq[14] feeds TRELLIS_IO TRELLIS_IO_14, removing $nextpnr_ibuf sdram_dq[14]. Info: pin 'TRELLIS_IO_14' constrained to Bel 'X90/Y29/PIOC'. Info: sdram_dq[15] feeds TRELLIS_IO TRELLIS_IO_15, removing $nextpnr_ibuf sdram_dq[15]. Info: pin 'TRELLIS_IO_15' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X90/Y62/PIOC'. Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X90/Y62/PIOB'. Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X90/Y65/PIOA'. Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X90/Y62/PIOA'. Info: pin 'sdram_cke$tr_io' constrained to Bel 'X90/Y26/PIOC'. Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X90/Y59/PIOC'. Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X90/Y59/PIOB'. Info: pin 'sdram_dm[0]$tr_io' constrained to Bel 'X90/Y65/PIOC'. Info: pin 'sdram_dm[1]$tr_io' constrained to Bel 'X90/Y26/PIOA'. Info: Packing constants.. Info: Packing carries... Info: Finding LUTFF pairs... Info: Packing LUT5-7s... Info: Finding LUT-LUT pairs... Info: Packing paired LUTs into a SLICE... Info: Packing unpaired LUTs into a SLICE... Info: Packing unpaired FFs into a SLICE... Info: Generating derived timing constraints... Info: Input frequency of PLL 'EHXPLLL' is constrained to 25.0 MHz Info: Derived frequency constraint of 50.0 MHz for net main_soclinux_clkout0 Info: Derived frequency constraint of 50.0 MHz for net sdram_clock Info: Promoting globals... Info: promoting clock net main_soclinux_clkout0 to global network Info: promoting clock net sdram_clock to global network Info: Checksum: 0x9be7b2c4

Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0xdb681f54

Info: Device utilisation: Info: TRELLIS_SLICE: 8299/21924 37% Info: TRELLIS_IO: 44/ 244 18% Info: DCCA: 2/ 56 3% Info: DP16KD: 45/ 108 41% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 1/ 4 25% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 84 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 8 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0%

Info: Placed 45 cells based on constraints. Info: Creating initial analytic placement for 7216 cells, random placement wirelen = 747878. Info: at initial placer iter 0, wirelen = 3690 Info: at initial placer iter 1, wirelen = 3367 Info: at initial placer iter 2, wirelen = 3451 Info: at initial placer iter 3, wirelen = 3472 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 3401, spread = 135430, legal = 138958; time = 0.44s Info: at iteration #2, type ALL: wirelen solved = 15992, spread = 104766, legal = 107691; time = 0.49s Info: at iteration #3, type ALL: wirelen solved = 27080, spread = 95620, legal = 100244; time = 0.46s Info: at iteration #4, type ALL: wirelen solved = 34768, spread = 91469, legal = 95265; time = 0.49s Info: at iteration #5, type ALL: wirelen solved = 39322, spread = 86717, legal = 91313; time = 0.47s Info: at iteration #6, type ALL: wirelen solved = 43076, spread = 85263, legal = 88532; time = 0.46s Info: at iteration #7, type ALL: wirelen solved = 47079, spread = 82991, legal = 87313; time = 0.46s Info: at iteration #8, type ALL: wirelen solved = 48502, spread = 80196, legal = 84361; time = 0.45s Info: at iteration #9, type ALL: wirelen solved = 49667, spread = 81517, legal = 85279; time = 0.45s Info: at iteration #10, type ALL: wirelen solved = 51946, spread = 80979, legal = 85671; time = 0.45s Info: at iteration #11, type ALL: wirelen solved = 53191, spread = 80380, legal = 85838; time = 0.45s Info: at iteration #12, type ALL: wirelen solved = 54511, spread = 80378, legal = 86168; time = 0.45s Info: at iteration #13, type ALL: wirelen solved = 55318, spread = 79152, legal = 85403; time = 0.48s Info: HeAP Placer Time: 11.82s Info: of which solving equations: 5.40s Info: of which spreading cells: 0.95s Info: of which strict legalisation: 0.29s

Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 2208, wirelen = 84361 Info: at iteration #5: temp = 0.000000, timing cost = 1124, wirelen = 75377 Info: at iteration #10: temp = 0.000000, timing cost = 1337, wirelen = 73461 Info: at iteration #15: temp = 0.000000, timing cost = 1274, wirelen = 73052 Info: at iteration #20: temp = 0.000000, timing cost = 1220, wirelen = 72882 Info: at iteration #25: temp = 0.000000, timing cost = 1255, wirelen = 72808 Info: at iteration #26: temp = 0.000000, timing cost = 1253, wirelen = 72794 Info: SA placement time 49.53s

Info: Max frequency for clock '$glbnet$main_soclinux_clkout0': 29.29 MHz (FAIL at 50.00 MHz)

Info: Max delay -> posedge $glbnet$main_soclinux_clkout0: 11.21 ns Info: Max delay posedge $glbnet$main_soclinux_clkout0 -> : 8.69 ns

Info: Slack histogram: Info: legend: represents 32 endpoint(s) Info: + represents [1,32) endpoint(s) Info: [-14143, -9405) |+ Info: [ -9405, -4667) |**+ Info: [ -4667, 71) |*+ Info: [ 71, 4809) |**** Info: [ 4809, 9547) |**+ Info: [ 9547, 14285) |***+ Info: [ 14285, 19023) |**+ Info: [ 19023, 23761) | Info: [ 23761, 28499) | Info: [ 28499, 33237) | Info: [ 33237, 37975) | Info: [ 37975, 42713) | Info: [ 42713, 47451) | Info: [ 47451, 52189) | Info: [ 52189, 56927) | Info: [ 56927, 61665) | Info: [ 61665, 66403) | Info: [ 66403, 71141) | Info: [ 71141, 75879) |+ Info: [ 75879, 80617) |*+ Info: Checksum: 0x64ec61da Info: Routing globals... Info: routing clock net $glbnet$main_soclinux_clkout0 using global 0 Info: routing clock net $glbnet$sdram_clock using global 1

Info: Routing.. Info: Setting up routing queue. Info: Routing 52374 arcs. Info: | (re-)routed arcs | delta | remaining Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs Info: 1000 | 36 963 | 36 963 | 51531 Info: 2000 | 115 1884 | 79 921 | 50931 Info: 3000 | 206 2793 | 91 909 | 50443 Info: 4000 | 238 3761 | 32 968 | 49534 Info: 5000 | 272 4727 | 34 966 | 48673 Info: 6000 | 340 5659 | 68 932 | 47914 Info: 7000 | 391 6608 | 51 949 | 47173 Info: 8000 | 453 7546 | 62 938 | 46440 Info: 9000 | 549 8450 | 96 904 | 45862 Info: 10000 | 597 9402 | 48 952 | 45119 Info: 11000 | 730 10269 | 133 867 | 44723 Info: 12000 | 805 11194 | 75 925 | 44101 Info: 13000 | 871 12128 | 66 934 | 43318 Info: 14000 | 928 13071 | 57 943 | 42510 Info: 15000 | 935 14064 | 7 993 | 41519 Info: 16000 | 972 15027 | 37 963 | 40615 Info: 17000 | 1013 15986 | 41 959 | 39820 Info: 18000 | 1058 16941 | 45 955 | 38999 Info: 19000 | 1115 17884 | 57 943 | 38247 Info: 20000 | 1159 18840 | 44 956 | 37414 Info: 21000 | 1230 19769 | 71 929 | 36693 Info: 22000 | 1268 20731 | 38 962 | 35883 Info: 23000 | 1295 21704 | 27 973 | 34944 Info: 24000 | 1352 22647 | 57 943 | 34404 Info: 25000 | 1430 23569 | 78 922 | 33650 Info: 26000 | 1474 24525 | 44 956 | 32738 Info: 27000 | 1524 25475 | 50 950 | 31944 Info: 28000 | 1580 26419 | 56 944 | 31064 Info: 29000 | 1634 27365 | 54 946 | 30194 Info: 30000 | 1709 28290 | 75 925 | 29311 Info: 31000 | 1784 29215 | 75 925 | 28571 Info: 32000 | 1883 30116 | 99 901 | 27847 Info: 33000 | 1968 31031 | 85 915 | 27044 Info: 34000 | 2090 31909 | 122 878 | 26270 Info: 35000 | 2185 32814 | 95 905 | 25466 Info: 36000 | 2264 33735 | 79 921 | 24612 Info: 37000 | 2353 34646 | 89 911 | 23810 Info: 38000 | 2506 35493 | 153 847 | 23203 Info: 39000 | 2679 36320 | 173 827 | 22750 Info: 40000 | 2894 37105 | 215 785 | 22589 Info: 41000 | 3036 37963 | 142 858 | 22103 Info: 42000 | 3181 38818 | 145 855 | 21501 Info: 43000 | 3259 39740 | 78 922 | 20692 Info: 44000 | 3384 40615 | 125 875 | 20075 Info: 45000 | 3497 41502 | 113 887 | 19342 Info: 46000 | 3613 42386 | 116 884 | 18746 Info: 47000 | 3818 43181 | 205 795 | 18368 Info: 48000 | 3929 44070 | 111 889 | 17649 Info: 49000 | 4048 44951 | 119 881 | 16976 Info: 50000 | 4302 45697 | 254 746 | 16709 Info: 51000 | 4517 46482 | 215 785 | 16497 Info: 52000 | 4697 47302 | 180 820 | 16003 Info: 53000 | 4872 48127 | 175 825 | 15638 Info: 54000 | 5113 48886 | 241 759 | 15377 Info: 55000 | 5316 49683 | 203 797 | 14978 Info: 56000 | 5569 50430 | 253 747 | 14821 Info: 57000 | 5772 51227 | 203 797 | 14508 Info: 58000 | 6016 51983 | 244 756 | 14310 Info: 59000 | 6189 52810 | 173 827 | 13680 Info: 60000 | 6399 53600 | 210 790 | 13173 Info: 61000 | 6659 54340 | 260 740 | 12828 Info: 62000 | 6873 55126 | 214 786 | 12504 Info: 63000 | 7101 55898 | 228 772 | 12123 Info: 64000 | 7301 56698 | 200 800 | 11713 Info: 65000 | 7475 57524 | 174 826 | 11197 Info: 66000 | 7610 58389 | 135 865 | 10560 Info: 67000 | 7780 59219 | 170 830 | 10057 Info: 68000 | 7987 60012 | 207 793 | 9686 Info: 69000 | 8174 60825 | 187 813 | 9280 Info: 70000 | 8371 61628 | 197 803 | 8860 Info: 71000 | 8557 62442 | 186 814 | 8330 Info: 72000 | 8741 63258 | 184 816 | 7836 Info: 73000 | 8968 64031 | 227 773 | 7566 Info: 74000 | 9056 64943 | 88 912 | 6804 Info: 75000 | 9252 65747 | 196 804 | 6392 Info: 76000 | 9449 66550 | 197 803 | 6124 Info: 77000 | 9651 67348 | 202 798 | 5822 Info: 78000 | 9906 68093 | 255 745 | 5489 Info: 79000 | 10232 68767 | 326 674 | 5405 Info: 80000 | 10553 69446 | 321 679 | 5291 Info: 81000 | 10777 70222 | 224 776 | 4895 Info: 82000 | 11064 70935 | 287 713 | 4781 Info: 83000 | 11317 71682 | 253 747 | 4577 Info: 84000 | 11508 72491 | 191 809 | 4013 Info: 85000 | 11697 73302 | 189 811 | 3622 Info: 86000 | 11943 74056 | 246 754 | 3402 Info: 87000 | 12200 74799 | 257 743 | 3162 Info: 88000 | 12451 75548 | 251 749 | 2919 Info: 89000 | 12718 76281 | 267 733 | 2675 Info: 90000 | 12989 77010 | 271 729 | 2518 Info: 91000 | 13261 77738 | 272 728 | 2408 Info: 92000 | 13578 78421 | 317 683 | 2423 Info: 93000 | 13861 79138 | 283 717 | 2256 Info: 94000 | 14146 79853 | 285 715 | 1990 Info: 95000 | 14450 80549 | 304 696 | 1783 Info: 96000 | 14733 81266 | 283 717 | 1578 Info: 97000 | 15042 81957 | 309 691 | 1360 Info: 98000 | 15317 82682 | 275 725 | 937 Info: 99000 | 15378 83621 | 61 939 | 35 Info: 99034 | 15378 83656 | 0 35 | 0 Info: Routing complete. Info: Route time 103.08s Info: Checksum: 0xcd254ab3

Info: Critical path report for clock '$glbnet$main_soclinux_clkout0' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source $auto$simplemap.cc:420:simplemap_dff$22213_SLICE.Q0 Info: 2.6 3.2 Net VexRiscv.CsrPlugin_selfException_payload_badAddr[13] budget 1.131000 ns (59,31) -> (42,21) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$106801_SLICE.A1 Info: 0.2 3.4 Source $abc$102343$auto$blifparse.cc:492:parse_blif$106801_SLICE.F1 Info: 2.0 5.4 Net $abc$102343$auto$simplemap.cc:127:simplemap_reduce$31744_inv budget 1.131000 ns (42,21) -> (37,14) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$106830_SLICE.B0 Info: 0.2 5.7 Source $abc$102343$auto$blifparse.cc:492:parse_blif$106830_SLICE.F0 Info: 4.5 10.2 Net $abc$102343$auto$maccmap.cc:114:fulladd$19623.t1[32] budget 1.131000 ns (37,14) -> (83,16) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$107554_SLICE.B1 Info: 0.2 10.4 Source $abc$102343$auto$blifparse.cc:492:parse_blif$107554_SLICE.F1 Info: 0.4 10.8 Net $abc$102343$auto$maccmap.cc:114:fulladd$19578.t2[16] budget 1.131000 ns (83,16) -> (83,16) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$107553_SLICE.D0 Info: 0.2 11.0 Source $abc$102343$auto$blifparse.cc:492:parse_blif$107553_SLICE.F0 Info: 0.8 11.9 Net $abc$102343$auto$maccmap.cc:112:fulladd$19577[16]_inv budget 1.131000 ns (83,16) -> (83,16) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$107551_SLICE.A1 Info: 0.2 12.1 Source $abc$102343$auto$blifparse.cc:492:parse_blif$107551_SLICE.F1 Info: 1.1 13.2 Net $abc$102343$auto$maccmap.cc:114:fulladd$19596.t1[17] budget 1.131000 ns (83,16) -> (82,15) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$107558_SLICE.A1 Info: 0.2 13.5 Source $abc$102343$auto$blifparse.cc:492:parse_blif$107558_SLICE.F1 Info: 0.9 14.4 Net $abc$102343$auto$maccmap.cc:111:fulladd$19594[17] budget 1.131000 ns (82,15) -> (81,16) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$107586.mux53_SLICE.A1 Info: 0.4 14.8 Source $abc$102343$auto$blifparse.cc:492:parse_blif$107586.mux53_SLICE.OFX0 Info: 0.0 14.8 Net $abc$102343$auto$blifparse.cc:492:parse_blif$107586.g3 budget 0.000000 ns (81,16) -> (81,16) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$107586.mux53_SLICE.FXB Info: 0.2 15.0 Source $abc$102343$auto$blifparse.cc:492:parse_blif$107586.mux53_SLICE.OFX1 Info: 0.0 15.0 Net $abc$102343$auto$blifparse.cc:492:parse_blif$107586.h1 budget 0.000000 ns (81,16) -> (81,16) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$107586.mux52_SLICE.FXB Info: 0.2 15.3 Source $abc$102343$auto$blifparse.cc:492:parse_blif$107586.mux52_SLICE.OFX1 Info: 2.3 17.5 Net $abc$102343$auto$maccmap.cc:111:fulladd$19612[18] budget 1.583000 ns (81,16) -> (78,19) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$109489.mux51_SLICE.B1 Info: 0.4 17.9 Source $abc$102343$auto$blifparse.cc:492:parse_blif$109489.mux51_SLICE.OFX0 Info: 0.0 17.9 Net $abc$102343$auto$blifparse.cc:492:parse_blif$109489.g1 budget 0.000000 ns (78,19) -> (78,19) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$109489.mux51_SLICE.FXB Info: 0.2 18.2 Source $abc$102343$auto$blifparse.cc:492:parse_blif$109489.mux51_SLICE.OFX1 Info: 0.0 18.2 Net $abc$102343$auto$blifparse.cc:492:parse_blif$109489.h0 budget 0.000000 ns (78,19) -> (78,19) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$109489.mux52_SLICE.FXA Info: 0.2 18.4 Source $abc$102343$auto$blifparse.cc:492:parse_blif$109489.mux52_SLICE.OFX1 Info: 2.0 20.4 Net $abc$102343$auto$maccmap.cc:111:fulladd$19621[19] budget 1.583000 ns (78,19) -> (67,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[18].ccu2c_i$CCU2_SLICE.A1 Info: 0.4 20.9 Source $auto$maccmap.cc:240:synth$19624.slice[18].ccu2c_i$CCU2_SLICE.FCO Info: 0.0 20.9 Net $auto$maccmap.cc:240:synth$19624.C[20] budget 0.000000 ns (67,24) -> (67,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[20].ccu2c_i$CCU2_SLICE.FCI Info: 0.1 20.9 Source $auto$maccmap.cc:240:synth$19624.slice[20].ccu2c_i$CCU2_SLICE.FCO Info: 0.0 20.9 Net $auto$maccmap.cc:240:synth$19624.C[22] budget 0.000000 ns (67,24) -> (68,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[22].ccu2c_i$CCU2_SLICE.FCI Info: 0.1 21.0 Source $auto$maccmap.cc:240:synth$19624.slice[22].ccu2c_i$CCU2_SLICE.FCO Info: 0.0 21.0 Net $auto$maccmap.cc:240:synth$19624.C[24] budget 0.000000 ns (68,24) -> (68,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[24].ccu2c_i$CCU2_SLICE.FCI Info: 0.1 21.1 Source $auto$maccmap.cc:240:synth$19624.slice[24].ccu2c_i$CCU2_SLICE.FCO Info: 0.0 21.1 Net $auto$maccmap.cc:240:synth$19624.C[26] budget 0.000000 ns (68,24) -> (68,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[26].ccu2c_i$CCU2_SLICE.FCI Info: 0.1 21.2 Source $auto$maccmap.cc:240:synth$19624.slice[26].ccu2c_i$CCU2_SLICE.FCO Info: 0.0 21.2 Net $auto$maccmap.cc:240:synth$19624.C[28] budget 0.000000 ns (68,24) -> (68,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[28].ccu2c_i$CCU2_SLICE.FCI Info: 0.1 21.2 Source $auto$maccmap.cc:240:synth$19624.slice[28].ccu2c_i$CCU2_SLICE.FCO Info: 0.0 21.2 Net $auto$maccmap.cc:240:synth$19624.C[30] budget 0.000000 ns (68,24) -> (69,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[30].ccu2c_i$CCU2_SLICE.FCI Info: 0.1 21.3 Source $auto$maccmap.cc:240:synth$19624.slice[30].ccu2c_i$CCU2_SLICE.FCO Info: 0.0 21.3 Net $auto$maccmap.cc:240:synth$19624.C[32] budget 0.000000 ns (69,24) -> (69,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[32].ccu2c_i$CCU2_SLICE.FCI Info: 0.5 21.8 Source $auto$maccmap.cc:240:synth$19624.slice[32].ccu2c_i$CCU2_SLICE.F1 Info: 0.1 21.9 Net VexRiscv._zz30[33] budget 3.694000 ns (69,24) -> (69,24) Info: Sink $auto$maccmap.cc:240:synth$19624.slice[32].ccu2c_i$CCU2_SLICE.DI1 Info: 0.0 21.9 Setup $auto$maccmap.cc:240:synth$19624.slice[32].ccu2c_i$CCU2_SLICE.DI1 Info: 5.1 ns logic, 16.9 ns routing

Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$main_soclinux_clkout0': Info: curr total Info: 0.0 0.0 Source rst$tr_io.O Info: 4.1 4.1 Net rst budget 19.576000 ns (4,71) -> (30,30) Info: Sink FD1S3BX_SLICE.LSR Info: 0.4 4.5 Setup FD1S3BX_SLICE.LSR Info: 0.4 ns logic, 4.1 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$main_soclinux_clkout0' -> '': Info: curr total Info: 0.5 0.5 Source $abc$102343$auto$blifparse.cc:492:parse_blif$103022_SLICE.Q0 Info: 0.9 1.4 Net main_soclinux_dq_oe budget 41.285999 ns (82,45) -> (82,45) Info: Sink $abc$102343$auto$blifparse.cc:492:parse_blif$103022_SLICE.A1 Info: 0.2 1.7 Source $abc$102343$auto$blifparse.cc:492:parse_blif$103022_SLICE.F1 Info: 2.6 4.2 Net $abc$102343$not$/home/phuong/Workspace/Projects/LITEX/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5161$1271_Y budget 41.285999 ns (82,45) -> (90,68) Info: Sink TRELLIS_IO_6.T Info: 0.8 ns logic, 3.5 ns routing

ERROR: Max frequency for clock '$glbnet$main_soclinux_clkout0': 45.65 MHz (FAIL at 50.00 MHz)

Info: Max delay -> posedge $glbnet$main_soclinux_clkout0: 4.53 ns Info: Max delay posedge $glbnet$main_soclinux_clkout0 -> : 4.24 ns

Info: Slack histogram: Info: legend: * represents 40 endpoint(s) Info: + represents [1,40) endpoint(s) Info: [ -1908, 2272) |+ Info: [ 2272, 6452) |**+ Info: [ 6452, 10632) |***+ Info: [ 10632, 14812) |****+ Info: [ 14812, 18992) |**** Info: [ 18992, 23172) |+ Info: [ 23172, 27352) | Info: [ 27352, 31532) | Info: [ 31532, 35712) | Info: [ 35712, 39892) | Info: [ 39892, 44072) | Info: [ 44072, 48252) | Info: [ 48252, 52432) | Info: [ 52432, 56612) | Info: [ 56612, 60792) | Info: [ 60792, 64972) | Info: [ 64972, 69152) | Info: [ 69152, 73332) | Info: [ 73332, 77512) | Info: [ 77512, 81692) |*+ 0 warnings, 1 error Traceback (most recent call last): File "./make.py", line 230, in main() File "./make.py", line 221, in main builder.build() File "/home/phuong/Workspace/Projects/LITEX/linux-on-litex-vexriscv/litex/litex/soc/integration/builder.py", line 171, in build toolchain_path=toolchain_path, kwargs) File "/home/phuong/Workspace/Projects/LITEX/linux-on-litex-vexriscv/litex/litex/soc/integration/soc_core.py", line 533, in build return self.platform.build(self, *args, *kwargs) File "/home/phuong/Workspace/Projects/LITEX/linux-on-litex-vexriscv/litex/litex/build/lattice/platform.py", line 29, in build return self.toolchain.build(self, args, **kwargs) File "/home/phuong/Workspace/Projects/LITEX/linux-on-litex-vexriscv/litex/litex/build/lattice/trellis.py", line 193, in build _run_script(script) File "/home/phuong/Workspace/Projects/LITEX/linux-on-litex-vexriscv/litex/litex/build/lattice/trellis.py", line 106, in _run_script raise OSError("Subprocess failed") OSError: Subprocess failed phuong@ubuntu1604lts:~/Workspace/Projects/LITEX/linux-on-litex-vexriscv$

Dolu1990 commented 5 years ago

@kamejoko80 that timing issue is weird. Did you tried to synthetise on the vendor tool too get its FMax ? Just to figure out if that's a nextpnr-ecp5 issue or a RTL design issue ?

kamejoko80 commented 5 years ago

@Dolu1990 Thanks for your reply.

For board ulx3s, there is a hardcode defined toolchain trellis in make.py @line 196 I changed to: soc_kwargs["toolchain"] = "diamond" However, my Linux version of diamond tool didn't work, I used the windows version and compiled the generated Verilog files.

Timing error report seems to be persisted below is the log:

PAR: Place And Route Diamond (64-bit) 3.11.0.396.4. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Fri Jun 07 23:00:07 2019

Z:/FOSSIL/ProgramFiles/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f ulx3s_impl1.p2t ulx3s_impl1_map.ncd ulx3s_impl1.dir ulx3s_impl1.prf -gui

Preference file: ulx3s_impl1.prf.

Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status

5_1 * 0 -2.233 4218904 0.160 0 02:36 Completed

Total (real) run time for 1-seed: 2 mins 37 secs

par done!

Note: user must run 'Trace' for timing closure signoff.

Lattice Place and Route Report for Design "ulx3s_impl1_map.ncd" Fri Jun 07 23:00:07 2019

Best Par Run PAR: Place And Route Diamond (64-bit) 3.11.0.396.4. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF ulx3s_impl1_map.ncd ulx3s_impl1.dir/5_1.ncd ulx3s_impl1.prf Preference file: ulx3s_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6

Loading design for application par from file ulx3s_impl1_map.ncd. Design name: top NCD version: 3.3 Vendor: LATTICE Device: LFE5U-45F Package: CABGA381 Performance: 6 Loading device for application par from file 'sa5p45.nph' in environment: Z:/FOSSIL/ProgramFiles/lscc/diamond/3.11_x64/ispfpga. Package Status: Final Version 1.43. Performance Hardware Data Status: Final Version 55.1. License checked out.

Ignore Preference Error(s): True

Device utilization summary:

PIO (prelim) 44/245 17% used 44/203 21% bonded IOLOGIC 38/245 15% used

SLICE 4267/21924 19% used

GSR 1/1 100% used EBR 29/108 26% used PLL 1/4 25% used MULT18 7/72 9% used ALU54 3/36 8% used

Number of Signals: 10567 Number of Connections: 31219

Pin Constraint Summary: 44 out of 44 pins locked (100% locked).

The following 2 signals are selected to use the primary clock routing resources: sys_clk (driver: EHXPLLL, clk/ce/sr load #: 1977/0/0) sys_ps_clk (driver: EHXPLLL, clk/ce/sr load #: 16/0/0)

Signal rst_c is selected as Global Set/Reset. Starting Placer Phase 0. ........... Finished Placer Phase 0. REAL time: 18 secs

Starting Placer Phase 1. ........................... Placer score = 4987435. Finished Placer Phase 1. REAL time: 52 secs

Starting Placer Phase 2. . Placer score = 4875716 Finished Placer Phase 2. REAL time: 1 mins

Clock Report

Global Clock Resources: CLK_PIN : 0 out of 12 (0%) GR_PCLK : 0 out of 12 (0%) PLL : 1 out of 4 (25%) DCS : 0 out of 2 (0%) DCC : 0 out of 60 (0%) CLKDIV : 0 out of 4 (0%)

Quadrant TL Clocks: PRIMARY "sys_clk" from CLKOP on comp "EHXPLLL" on PLL site "PLL_BL0", CLK/CE/SR load = 53

PRIMARY : 1 out of 16 (6%)

Quadrant TR Clocks: PRIMARY "sys_clk" from CLKOP on comp "EHXPLLL" on PLL site "PLL_BL0", CLK/CE/SR load = 669 PRIMARY "sys_ps_clk" from CLKOS on comp "EHXPLLL" on PLL site "PLL_BL0", CLK/CE/SR load = 9

PRIMARY : 2 out of 16 (12%)

Quadrant BL Clocks: PRIMARY "sys_clk" from CLKOP on comp "EHXPLLL" on PLL site "PLL_BL0", CLK/CE/SR load = 453

PRIMARY : 1 out of 16 (6%)

Quadrant BR Clocks: PRIMARY "sys_clk" from CLKOP on comp "EHXPLLL" on PLL site "PLL_BL0", CLK/CE/SR load = 802 PRIMARY "sys_ps_clk" from CLKOS on comp "EHXPLLL" on PLL site "PLL_BL0", CLK/CE/SR load = 7

PRIMARY : 2 out of 16 (12%)

Edge Clocks:

No edge clock selected.

+ I/O Usage Summary (final): 44 out of 245 (18.0%) PIO sites used. 44 out of 203 (21.7%) bonded PIO sites used. Number of PIO comps: 44; differential: 0. Number of Vref pins used: 0.

I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 0 / 27 ( 0%) | - | - | - | | 1 | 0 / 33 ( 0%) | - | - | - | | 2 | 20 / 32 ( 62%) | 3.3V | - | - | | 3 | 19 / 33 ( 57%) | 3.3V | - | - | | 6 | 4 / 33 ( 12%) | 3.3V | - | - | | 7 | 0 / 32 ( 0%) | - | - | - | | 8 | 1 / 13 ( 7%) | 2.5V | - | - | +----------+----------------+------------+------------+------------+

---------------------------------- DSP Report ----------------------------------

DSP Slice #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

of MULT9

of MULT18 2 2 1 2

of ALU24

of ALU54 1 1 1

of PRADD9

of PRADD18

DSP Slice #: 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

of MULT9

of MULT18

of ALU24

of ALU54

of PRADD9

of PRADD18

DSP Slice 10 Component_Type Physical_Type Instance_Name
MULT18_R22C46 MULT18X18D MULT18 VexRiscv/_zz29[0:35]
MULT18_R22C47 MULT18X18D MULT18 VexRiscv/_zz29[18:53]
ALU54_R22C49 ALU54B ALU54 VexRiscv/_zz_29__add[0:53]

DSP Slice 11 Component_Type Physical_Type Instance_Name
MULT18_R22C51 MULT18X18D MULT18 VexRiscv/_zz30[0:35]
MULT18_R22C52 MULT18X18D MULT18 VexRiscv/_zz30[18:53]
ALU54_R22C54 ALU54B ALU54 VexRiscv/_zz_30__add[0:53]

DSP Slice 12 Component_Type Physical_Type Instance_Name
MULT18_R22C55 MULT18X18D MULT18 VexRiscv/_zz31[31:0]

DSP Slice 13 Component_Type Physical_Type Instance_Name
MULT18_R22C60 MULT18X18D MULT18 VexRiscv/_zz28[33:0]
MULT18_R22C61 MULT18X18D MULT18 VexRiscv/writeBack_MulPlugin_result_pt
ALU54_R22C63 ALU54B ALU54 VexRiscv/writeBack_MulPlugin_result[63:32]

------------------------------ End of DSP Report ------------------------------- Total placer CPU time: 54 secs

Dumping design to file ulx3s_impl1.dir/5_1.ncd.

0 connections routed; 31219 unrouted. Starting router resource preassignment DSP info: No dsp pins have been swapped.

Completed router resource preassignment. Real time: 1 mins 9 secs

Start NBR router at 23:01:17 06/07/19

Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify
your design.

Start NBR special constraint process at 23:01:19 06/07/19

Start NBR section for initial routing at 23:01:20 06/07/19 Level 1, iteration 1 715(0.03%) conflicts; 24482(78.42%) untouched conns; 4117405 (nbr) score; Estimated worst slack/total negative slack: -2.554ns/-4117.406ns; real time: 1 mins 20 secs Level 2, iteration 1 1330(0.06%) conflicts; 19182(61.44%) untouched conns; 2091841 (nbr) score; Estimated worst slack/total negative slack: -2.956ns/-2091.842ns; real time: 1 mins 37 secs Level 3, iteration 1 1215(0.06%) conflicts; 9600(30.75%) untouched conns; 2569853 (nbr) score; Estimated worst slack/total negative slack: -2.416ns/-2569.853ns; real time: 1 mins 42 secs Level 4, iteration 1 1808(0.09%) conflicts; 0(0.00%) untouched conn; 2218676 (nbr) score; Estimated worst slack/total negative slack: -2.374ns/-2218.676ns; real time: 1 mins 49 secs

Info: Initial congestion level at 75% usage is 1 Info: Initial congestion area at 75% usage is 44 (0.72%)

Start NBR section for normal routing at 23:01:56 06/07/19 Level 1, iteration 1 704(0.03%) conflicts; 1720(5.51%) untouched conns; 1479778 (nbr) score; Estimated worst slack/total negative slack: -1.639ns/-1479.779ns; real time: 1 mins 51 secs Level 1, iteration 2 520(0.02%) conflicts; 2125(6.81%) untouched conns; 1299521 (nbr) score; Estimated worst slack/total negative slack: -1.672ns/-1299.521ns; real time: 1 mins 54 secs Level 1, iteration 3 379(0.02%) conflicts; 2358(7.55%) untouched conns; 1356316 (nbr) score; Estimated worst slack/total negative slack: -1.662ns/-1356.316ns; real time: 1 mins 56 secs Level 1, iteration 4 259(0.01%) conflicts; 2574(8.24%) untouched conns; 1356316 (nbr) score; Estimated worst slack/total negative slack: -1.662ns/-1356.316ns; real time: 1 mins 58 secs Level 1, iteration 5 146(0.01%) conflicts; 2708(8.67%) untouched conns; 1570326 (nbr) score; Estimated worst slack/total negative slack: -1.666ns/-1570.326ns; real time: 1 mins 59 secs Level 1, iteration 6 133(0.01%) conflicts; 2725(8.73%) untouched conns; 1570326 (nbr) score; Estimated worst slack/total negative slack: -1.666ns/-1570.326ns; real time: 2 mins Level 1, iteration 7 86(0.00%) conflicts; 2746(8.80%) untouched conns; 1760686 (nbr) score; Estimated worst slack/total negative slack: -1.719ns/-1760.686ns; real time: 2 mins 1 secs Level 1, iteration 8 89(0.00%) conflicts; 2758(8.83%) untouched conns; 1760686 (nbr) score; Estimated worst slack/total negative slack: -1.719ns/-1760.686ns; real time: 2 mins 2 secs Level 1, iteration 9 59(0.00%) conflicts; 2766(8.86%) untouched conns; 1736255 (nbr) score; Estimated worst slack/total negative slack: -1.666ns/-1736.255ns; real time: 2 mins 3 secs Level 1, iteration 10 63(0.00%) conflicts; 2770(8.87%) untouched conns; 1736255 (nbr) score; Estimated worst slack/total negative slack: -1.666ns/-1736.255ns; real time: 2 mins 4 secs Level 1, iteration 11 44(0.00%) conflicts; 2783(8.91%) untouched conns; 1840939 (nbr) score; Estimated worst slack/total negative slack: -2.046ns/-1840.939ns; real time: 2 mins 5 secs Level 1, iteration 12 40(0.00%) conflicts; 2796(8.96%) untouched conns; 1840939 (nbr) score; Estimated worst slack/total negative slack: -2.046ns/-1840.939ns; real time: 2 mins 5 secs Level 1, iteration 13 28(0.00%) conflicts; 2799(8.97%) untouched conns; 1941253 (nbr) score; Estimated worst slack/total negative slack: -2.070ns/-1941.253ns; real time: 2 mins 6 secs Level 1, iteration 14 30(0.00%) conflicts; 2792(8.94%) untouched conns; 1941253 (nbr) score; Estimated worst slack/total negative slack: -2.070ns/-1941.253ns; real time: 2 mins 7 secs Level 1, iteration 15 21(0.00%) conflicts; 2797(8.96%) untouched conns; 1883196 (nbr) score; Estimated worst slack/total negative slack: -2.054ns/-1883.196ns; real time: 2 mins 7 secs Level 1, iteration 16 22(0.00%) conflicts; 2799(8.97%) untouched conns; 1883196 (nbr) score; Estimated worst slack/total negative slack: -2.054ns/-1883.196ns; real time: 2 mins 8 secs Level 1, iteration 17 12(0.00%) conflicts; 2812(9.01%) untouched conns; 1949323 (nbr) score; Estimated worst slack/total negative slack: -2.422ns/-1949.323ns; real time: 2 mins 8 secs Level 1, iteration 18 22(0.00%) conflicts; 2809(9.00%) untouched conns; 1949323 (nbr) score; Estimated worst slack/total negative slack: -2.422ns/-1949.323ns; real time: 2 mins 9 secs Level 1, iteration 19 7(0.00%) conflicts; 2811(9.00%) untouched conns; 2080117 (nbr) score; Estimated worst slack/total negative slack: -2.430ns/-2080.117ns; real time: 2 mins 9 secs Level 1, iteration 20 12(0.00%) conflicts; 2810(9.00%) untouched conns; 2080117 (nbr) score; Estimated worst slack/total negative slack: -2.430ns/-2080.117ns; real time: 2 mins 10 secs Level 1, iteration 21 5(0.00%) conflicts; 2810(9.00%) untouched conns; 1958623 (nbr) score; Estimated worst slack/total negative slack: -2.422ns/-1958.623ns; real time: 2 mins 10 secs Level 4, iteration 1 533(0.03%) conflicts; 0(0.00%) untouched conn; 2038762 (nbr) score; Estimated worst slack/total negative slack: -2.444ns/-2038.762ns; real time: 2 mins 13 secs Level 4, iteration 2 223(0.01%) conflicts; 0(0.00%) untouched conn; 2062612 (nbr) score; Estimated worst slack/total negative slack: -2.444ns/-2062.612ns; real time: 2 mins 15 secs Level 4, iteration 3 90(0.00%) conflicts; 0(0.00%) untouched conn; 2105154 (nbr) score; Estimated worst slack/total negative slack: -2.444ns/-2105.154ns; real time: 2 mins 16 secs Level 4, iteration 4 49(0.00%) conflicts; 0(0.00%) untouched conn; 2105154 (nbr) score; Estimated worst slack/total negative slack: -2.444ns/-2105.154ns; real time: 2 mins 16 secs Level 4, iteration 5 27(0.00%) conflicts; 0(0.00%) untouched conn; 2141584 (nbr) score; Estimated worst slack/total negative slack: -2.436ns/-2141.584ns; real time: 2 mins 17 secs Level 4, iteration 6 13(0.00%) conflicts; 0(0.00%) untouched conn; 2141584 (nbr) score; Estimated worst slack/total negative slack: -2.436ns/-2141.584ns; real time: 2 mins 17 secs Level 4, iteration 7 4(0.00%) conflicts; 0(0.00%) untouched conn; 2148625 (nbr) score; Estimated worst slack/total negative slack: -2.436ns/-2148.625ns; real time: 2 mins 18 secs Level 4, iteration 8 3(0.00%) conflicts; 0(0.00%) untouched conn; 2148625 (nbr) score; Estimated worst slack/total negative slack: -2.436ns/-2148.625ns; real time: 2 mins 18 secs Level 4, iteration 9 0(0.00%) conflict; 0(0.00%) untouched conn; 2155155 (nbr) score; Estimated worst slack/total negative slack: -2.436ns/-2155.155ns; real time: 2 mins 18 secs

Start NBR section for performance tuning (iteration 1) at 23:02:25 06/07/19 Level 4, iteration 1 4(0.00%) conflicts; 0(0.00%) untouched conn; 2030280 (nbr) score; Estimated worst slack/total negative slack: -1.873ns/-2030.280ns; real time: 2 mins 19 secs Level 4, iteration 2 1(0.00%) conflict; 0(0.00%) untouched conn; 2123775 (nbr) score; Estimated worst slack/total negative slack: -2.187ns/-2123.775ns; real time: 2 mins 19 secs Level 4, iteration 3 1(0.00%) conflict; 0(0.00%) untouched conn; 2129527 (nbr) score; Estimated worst slack/total negative slack: -2.233ns/-2129.527ns; real time: 2 mins 19 secs Level 4, iteration 4 0(0.00%) conflict; 0(0.00%) untouched conn; 2129527 (nbr) score; Estimated worst slack/total negative slack: -2.233ns/-2129.527ns; real time: 2 mins 19 secs

Start NBR section for performance tuning (iteration 2) at 23:02:26 06/07/19 Level 4, iteration 1 1(0.00%) conflict; 0(0.00%) untouched conn; 2089634 (nbr) score; Estimated worst slack/total negative slack: -1.932ns/-2089.634ns; real time: 2 mins 20 secs Level 4, iteration 2 1(0.00%) conflict; 0(0.00%) untouched conn; 2124399 (nbr) score; Estimated worst slack/total negative slack: -2.187ns/-2124.399ns; real time: 2 mins 20 secs Level 4, iteration 3 0(0.00%) conflict; 0(0.00%) untouched conn; 2130492 (nbr) score; Estimated worst slack/total negative slack: -2.233ns/-2130.492ns; real time: 2 mins 20 secs

Start NBR section for re-routing at 23:02:27 06/07/19 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 2130492 (nbr) score; Estimated worst slack/total negative slack: -2.233ns/-2130.492ns; real time: 2 mins 21 secs

Start NBR section for post-routing at 23:02:28 06/07/19

End NBR router with 0 unrouted connection

NBR Summary

Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 3429 (10.98%) Estimated worst slack : -2.233ns Timing score : 4218904

Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.

Total CPU time 2 mins 20 secs Total REAL time: 2 mins 34 secs Completely routed. End of route. 31219 routed (100.00%); 0 unrouted.

Hold time timing score: 0, hold timing errors: 0

Timing score: 4218904

Dumping design to file ulx3s_impl1.dir/5_1.ncd.

All signals are completely routed.

PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/> = -2.233 PAR_SUMMARY::Timing score<setup/> = 4218.904 PAR_SUMMARY::Worst slack<hold /> = 0.160 PAR_SUMMARY::Timing score<hold /> = 0.000 PAR_SUMMARY::Number of errors = 0

Total CPU time to completion: 2 mins 23 secs Total REAL time to completion: 2 mins 37 secs

par done!

Note: user must run 'Trace' for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.

Dolu1990 commented 5 years ago

Hoooo. Maybe that's due to one change i made in the way the verilog is generated. Basicaly, now all combinatorial always blocks generated from SpinalHDL will only drive one signal. By the past, the generation was allowed to merge combinatorial always blocks which had in common some if statements. I tested on both Vivado, Quartus, and ice40 yosys, that seem to have no impact. But maybe i'm wrong. I will test on my setup.

enjoy-digital commented 5 years ago

I just tried rebuilding with upstream LiteX and last version of vexriscv-verilog and build is working fine: https://hastebin.com/iguxatibal.http

I'm going to update Yosys/NextPnr and see if it's also successful.

enjoy-digital commented 5 years ago

With upstream Yosys/Trellis/NextPnr it's also building fine: https://hastebin.com/cuhumiyuwa.http @kamejoko80 is everything up to date on your side?

kamejoko80 commented 5 years ago

@enjoy-digital

I installed the toolchains as below:

Yosys:

https://github.com/YosysHQ/yosys

Prjtrellis:

https://github.com/SymbiFlow/prjtrellis

Then nextpnr:

https://github.com/YosysHQ/nextpnr

Are there any special configurations before compiling and installing the toolchains?

enjoy-digital commented 5 years ago

@kamejoko80: just following the respective READMEs should be fine. Can you try executing build_top.sh in the attached archive and see if you have the same result (remove the .txt extension)?

gateware.tar.xz.txt

daveshah1 commented 5 years ago

10-15% could well be within inter-seed variation. So if there is any nondeterminism (slight tool version or database differences, differences in the Verilog even nonfunctional or library differences) then this might take the design from passing to failing (you can test this by passing a value other than 1 to the nextpnr --seed parameter). I have observed this behaviour with Diamond too.

Dolu1990 commented 5 years ago

What i could do to improve that specific critical path, is to pipeline the interrupt delegation / agregation. this would only cost something like 8 register + 1 cycle latency on interrupts

kamejoko80 commented 5 years ago

@enjoy-digital

I got the same error after running your build_top.sh. I've compared your gateware folder and mine, they are identical.

I've tried with @daveshah1's suggestion however it doesn't help.

Dolu1990 commented 5 years ago

@Kamejoko80 What is the critical path for you ? I just submited a MTIP relaxation fix

Dolu1990 commented 5 years ago

ahh but it look like litex isn't using the updated version (https://github.com/enjoy-digital/VexRiscv-verilog/blob/master/VexRiscv_Linux.v)

kamejoko80 commented 5 years ago

@Dolu1990

I've updated the repo in local and built again, but the same error happened. Have you already tried the command ./make.py --board=ulx3s --build ?

Dolu1990 commented 5 years ago

No no, don't worry, i have the same issue. Now i can reproduce it. I'm now looking how to relax that exact path.

Dolu1990 commented 5 years ago

I mean, one easy way would be to disable the static branch prediction in the VexRiscv config. for sure then the timings would be ok. But i'm trying to find a way to not having to do that

Dolu1990 commented 5 years ago

I think i have a good fix, but i need some time to check it work on all configs. Basicaly, avoiding that the branch prediction having to check that the instruction in the decode stage is allowed to go in the execute stage, which was adding much combinatorial path on the nextPC calculation

Actualy got Info: Max frequency for clock '$glbnet$main_soclinux_clkout0': 55.39 MHz (PASS at 50.00 MHz) I hope that's not only because of a lucky seed XD

I will let's you know when things are ok.

Dolu1990 commented 5 years ago

At the end, i reworked the whole CPU flush/pc calculation logic, and now it pass all the regressions tests. https://github.com/SpinalHDL/VexRiscv/commit/7c3c4e8c8126afe3b957a7779223fa8cdfcd660e#diff-04c6e90faac2675aa89e2176d2eec7d8R98

Will release it soon, Just need to release SpinalHDL with it to bringe jtag fixes

kamejoko80 commented 5 years ago

@Dolu1990

Sounds good Thanks

Dolu1990 commented 5 years ago

So, i updated VexRiscv verilog with a specific config : 

VexRiscv_LinuxNoDspFmax.v: $(SRC)
    sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --singleCycleMulDiv=false --relaxedPcCalculation=true --prediction=none --outputFile VexRiscv_LinuxNoDspFmax"

Mainly, relaxed PC calculation, and iterative mul div as currently, there is no DSP inferation in the open source flow for the ECP5.

@enjoy-digital This need to be integrated futher in the litex toolchain.

Does this seem good ?

I tried synthesis, and i get a good margin : Info: Max frequency for clock '$glbnet$main_soclinux_clkout0': 61.97 MHz (PASS at 50.00 MHz)

enjoy-digital commented 5 years ago

Thanks @Dolu1990, i integrated that and now also get good margins, @kamejoko80 if it's also fine for you, we can close this issue.

kamejoko80 commented 5 years ago

Thanks @Dolu1990

Confirmed that I'm able to synthesize and generate the bitstream for board ulx3s now.

I got the maximum clock frequency ~ 58.7MHz

Info: Max frequency for clock '$glbnet$main_soclinux_clkout0': 58.70 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$main_soclinux_clkout0: 4.20 ns Info: Max delay posedge $glbnet$main_soclinux_clkout0 -> : 4.63 ns

enjoy-digital commented 5 years ago

Good, thanks.