hyperbus: Fix byte enable ordering

litex-hub / litehyperbus

Small footprint and configurable HyperBus core

BSD 2-Clause "Simplified" License

10 stars 5 forks source link

hyperbus: Fix byte enable ordering #3

Closed daveshah1 closed 3 years ago

daveshah1 commented 3 years ago

Without this patch; when using HyperRAM as main SRAM on the LIFCL VIP; the serial output was garbled.

Not sure how this ever worked, but I'd be interested to know if there is something that I've missed here...

gregdavill commented 3 years ago

Thanks!

This core has only really been used on my Boson projects so far. There it's connected directly to some 32bit/cycle DMAs. So it's likely only 32bit words have been tested.

enjoy-digital commented 3 years ago

Thanks for catching this @daveshah1, I'm not sure byte enable ordering was tested on the minimal/generic core (IIRC we only tested it with 32-bit writes/reads).

gregdavill commented 3 years ago

Whoops, I should have checked what files were changed. I'd thought this was related to the ddrx2 core, not the generic one.