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litex-hub / litehyperbus

Small footprint and configurable HyperBus core
BSD 2-Clause "Simplified" License
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For efinix #7

Closed fjullien closed 2 years ago

fjullien commented 2 years ago

Not very happy with the changes. It complicates the code. At least it works.

fjullien commented 2 years ago

May be I could use a FSM like in hyperram_ddr2.py

enjoy-digital commented 2 years ago

Thanks @fjullien, it's generally not easy to get the simplest solution at first. Your PR looks good for me for this new 16-bit support.

To simplify it a bit without using an FSM, you could probably split dt_seq` in three parts:

This way you'll be able to minimize the specialization to the Write/Read access that only seems to be the specific parts.

This should already be simple enough to be merged. I'm sure we'll also see other possible simplification after this (especially on the ca/bus.adr part) but we could do them progressively.

fjullien commented 2 years ago

I updated the PR with your suggestions

enjoy-digital commented 2 years ago

Thanks @fjullien, this is merged.