Closed mithro closed 3 months ago
Hi @mithro. I have been trying to get memory-mapped (Q)SPI PSRAM working with LiteX for some time now with no success. I have some working Verilog for QSPI PSRAM in this repo: https://github.com/machdyne/qqspi
If anyone wants to attempt this I can probably provide a 32MB QSPI PSRAM PMOD.
I had this working in https://github.com/xobs/haddecks/blob/master/rtl/spi_ram.py, and I was working on interleaving access in https://github.com/xobs/haddecks/blob/master/rtl/spi_ram_dual.py
There are tests in https://github.com/xobs/haddecks/blob/master/sim/spiram.v
Thanks! This is working for me. I had to use dummy=6 with APS6404L-3SQR-SN PSRAM.
Maybe this can be merged into litex.soc.cores or litespi?
I have noticed a few boards with similar SPI PSRAM and with the QQSPI PMOD it's possible to add 32MB to any board with a PMOD socket, having this capability in LiteX might be useful, especially for the smaller boards.
I sucessfully integrated the PSRAM core from @xobs into a newer version of LiteX by patching the example SoC script, see https://github.com/litex-hub/micropython/commit/d7d2203cab9c2909395bbb5a9cff3d5016fa81a3
I think this is ready to go mainstream. Excellent core! It worked first time
This development makes the PSRAM appear as SPI flash https://github.com/litex-hub/litex-boards/pull/476/commits/b1df2c0f85fbcd5d4880ae71c05ac39b0abc4291
The HackADay badge has
These SPI SRAM chips, kinda look like SPI NOR chips.
It would be good to have these devices supported as memory mappable for both read and write.
Clock rate:
Datasheet -> https://www.electrodragon.com/w/images/0/04/LY68L6400_0.3.pdf