Open arunlee77 opened 10 months ago
@arunlee77: I'll do some test, it's possible some RAM or cache is too large and no longer fit on the embedded BRAM which then makes logic usage explode. This could eventually mean that this board is not suitable for Rocket (or could be, but with optimizations). To run Rocket without trouble, I would recommend checking the boards supported in Linux-on-LiteX-Rocket repository: https://github.com/litex-hub/linux-on-litex-rocket
Hi,
I am trying to build rocket chip for terasic de2115. There are some issues which i think some one with more knowledge on rocket support for de2115 could clarify more and suggest fixes.
I first raised the issue in https://github.com/litex-hub/linux-on-litex-rocket/issues/36
Build Command:
litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-variant linux --sys-clk-freq 50e6
But it generates the following error
Bulil Host:
Ubuntu 20.04
Quartus:
The question was posted to Quartus support and the response was as following:
I tried to Fix the error with the following change:
The line
`ifdef SYNTHESIS
to`ifndef SYNTHESIS
in filepythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v
.With this the build proceeded but Quartus again produced the following error
I tried building vexriscv and it proceeded without any error. So it looks to be an issue with the rocket with quartus.
Could anyone suggest what needs to be changed and how?
regards Arun