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Issues with cpu type rocket for terasic de2 115 #538

Open arunlee77 opened 1 year ago

arunlee77 commented 1 year ago

Hi,

I am trying to build rocket chip for terasic de2115. There are some issues which i think some one with more knowledge on rocket support for de2115 could clarify more and suggest fixes.

I first raised the issue in https://github.com/litex-hub/linux-on-litex-rocket/issues/36

Build Command:

litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-variant linux --sys-clk-freq 50e6

But it generates the following error

Info (12128): Elaborating entity "plusarg_reader" for hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error (10174): Verilog HDL Unsupported Feature error at plusarg_reader.v(22): system function "$value$plusargs" is not supported for synthesis File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v Line: 22
Error (12152): Can't elaborate user hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 329 warnings
    Error: Peak virtual memory: 852 megabytes
    Error: Processing ended: Wed Oct 11 22:46:26 2023
    Error: Elapsed time: 00:00:33
    Error: Total CPU time (on all processors): 00:00:49
Traceback (most recent call last):
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 90, in <module>
    main()
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 83, in main
    builder.build(**parser.toolchain_argdict)
  File "/home/arun/litex/litex/soc/integration/builder.py", line 367, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/arun/litex/litex/soc/integration/soc.py", line 1332, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/altera/platform.py", line 45, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/generic_toolchain.py", line 123, in build
    self.run_script(script)
  File "/home/arun/litex/litex/build/altera/quartus.py", line 216, in run_script
    raise OSError("Error occured during Quartus's script execution.")
OSError: Error occured during Quartus's script execution.

Bulil Host: Ubuntu 20.04

Quartus:

Quartus Prime Design Software
Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
Copyright (C) 2023  Intel Corporation. All rights reserved.

The question was posted to Quartus support and the response was as following:

Ok, so here is what I see in the core of that verilog module:

`ifdef SYNTHESIS
assign out = DEFAULT;
`else
reg [WIDTH-1:0] myplus;
assign out = myplus;

initial begin
   if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
end
`endif

and the error:

Error (10174): Verilog HDL Unsupported Feature error at plusarg_reader.v(22): system function "$value$plusargs" is not supported

which means that the compile variable SYNTHESIS is not set, so the code with the system task $value$plusargs() is being
fed into Quartus to compile. System tasks are in general not synthesizable constructs, so it throws the error, as expected.

You need to define SYNTHESIS to select the synthesizable code vs simulation code.

I tried to Fix the error with the following change:

The line`ifdef SYNTHESIS to `ifndef SYNTHESIS in file pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v.

With this the build proceeded but Quartus again produced the following error

Info (171121): Fitter preparation operations ending: elapsed time is 00:08:34
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Error (170011): Design contains 255036 blocks of type combinational node.  However, the device contains only 114480 blocks.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:01:40
Info (11888): Total time spent on timing analysis during the Fitter is 10.05 seconds.
Error (171000): Can't fit design in device
Warning (169177): 18 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin sdram_dq[0] uses I/O standard 3.3-V LVTTL at W3 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[1] uses I/O standard 3.3-V LVTTL at W2 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[2] uses I/O standard 3.3-V LVTTL at V4 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[3] uses I/O standard 3.3-V LVTTL at W1 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[4] uses I/O standard 3.3-V LVTTL at V3 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[5] uses I/O standard 3.3-V LVTTL at V2 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[6] uses I/O standard 3.3-V LVTTL at V1 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[7] uses I/O standard 3.3-V LVTTL at U3 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[8] uses I/O standard 3.3-V LVTTL at Y3 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[9] uses I/O standard 3.3-V LVTTL at Y4 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[10] uses I/O standard 3.3-V LVTTL at AB1 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[11] uses I/O standard 3.3-V LVTTL at AA3 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[12] uses I/O standard 3.3-V LVTTL at AB2 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[13] uses I/O standard 3.3-V LVTTL at AC1 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[14] uses I/O standard 3.3-V LVTTL at AB3 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin sdram_dq[15] uses I/O standard 3.3-V LVTTL at AC2 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 30
    Info (169178): Pin clk50 uses I/O standard 3.3-V LVTTL at Y2 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 22
    Info (169178): Pin serial_rx uses I/O standard 3.3-V LVTTL at G12 File: /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.v Line: 33
Info (144001): Generated suppressed messages file /home/arun/build/terasic_de2_115/gateware/terasic_de2_115.fit.smsg
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 6 warnings
    Error: Peak virtual memory: 4060 megabytes
    Error: Processing ended: Fri Oct 13 13:40:55 2023
    Error: Elapsed time: 00:15:36
    Error: Total CPU time (on all processors): 00:14:50
Traceback (most recent call last):
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 90, in <module>
    main()
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 83, in main
    builder.build(**parser.toolchain_argdict)
  File "/home/arun/litex/litex/soc/integration/builder.py", line 367, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/arun/litex/litex/soc/integration/soc.py", line 1332, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/altera/platform.py", line 45, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/generic_toolchain.py", line 123, in build
    self.run_script(script)
  File "/home/arun/litex/litex/build/altera/quartus.py", line 216, in run_script
    raise OSError("Error occured during Quartus's script execution.")
OSError: Error occured during Quartus's script execution.

I tried building vexriscv and it proceeded without any error. So it looks to be an issue with the rocket with quartus.

Could anyone suggest what needs to be changed and how?

regards Arun

enjoy-digital commented 10 months ago

@arunlee77: I'll do some test, it's possible some RAM or cache is too large and no longer fit on the embedded BRAM which then makes logic usage explode. This could eventually mean that this board is not suitable for Rocket (or could be, but with optimizations). To run Rocket without trouble, I would recommend checking the boards supported in Linux-on-LiteX-Rocket repository: https://github.com/litex-hub/linux-on-litex-rocket