Flash method since been implemented?

The linux-on-litex-vexriscv projects Board class has a flash method implemented. I'm trying to replicate that here, zephyr-on-litex-vexriscv. I figure since this repository hasn't seen recent updates and linux-on-litex-vexriscv has that the implementation would be very similar if not the same (let me know if I'm very wrong here).

The error I'm getting (Error: Unknown flash device (ID 0x00ffffff)) is outside of my understanding so I'm hoping someone could point me in the right direction.

Thanks

import argparse
import os

from litex.soc.integration.builder import Builder

from litespi.modules import *
from litespi.opcodes import SpiNorFlashOpCodes as Codes

from soc_zephyr import SoCZephyr

# Board definition----------------------------------------------------------------------------------

class Board:
    soc_kwargs = {"integrated_rom_size": 0xfa00}
    def __init__(self, soc_cls=None, soc_capabilities={}, soc_constants={}, bitstream_ext=""):
        self.soc_cls          = soc_cls
        self.soc_capabilities = soc_capabilities
        self.soc_constants    = soc_constants
        self.bitstream_ext    = bitstream_ext

    def load(self, filename):
        prog = self.platform.create_programmer()
        prog.load_bitstream(filename)

    def flash(self, filename):
        prog = self.platform.create_programmer()
        prog.flash(0, filename)

# Arty support -------------------------------------------------------------------------------------

class Arty(Board):
    spiflash = S25FL128L(Codes.READ_1_1_1)
    def __init__(self):
        from litex_boards.targets import arty
        Board.__init__(self, arty.BaseSoC, soc_capabilities={
            # Communication
            "serial",
            "ethernet",
            # Storage
            "spiflash",
            "sdcard",
            # GPIOs
            "leds",
            "rgb_led",
            "switches",
            # Buses
            "spi",
            "i2c",
            # Monitoring
            "xadc",
            # 7-Series specific
            "mmcm",
            "icap_bitstream",
        }, bitstream_ext=".bit")

# Main ---------------------------------------------------------------------------------------------

def main():
    parser = argparse.ArgumentParser(
        description="Zephyr on LiteX-VexRiscv\n\n",
        formatter_class=argparse.RawTextHelpFormatter
    )

    parser.add_argument(
        "--build",
        action="store_true",
        help="build bitstream"
    )

    parser.add_argument(
        "--toolchain",
        default=None,
        help="Toolchain use to build"
    )

    parser.add_argument(
        "--load",
        action="store_true",
        help="load bitstream (to SRAM). set path to bitstream"
    )

    parser.add_argument(
        "--flash",
        action="store_true",
        help="Flash bitstream/images (to SPI Flash)"
    )

    args = parser.parse_args()

    board = Arty()
    soc_kwargs = Board.soc_kwargs
    soc_kwargs.update(board.soc_kwargs)

    if args.toolchain is not None:
        soc_kwargs.update(toolchain=args.toolchain)

    soc = SoCZephyr(board.soc_cls, **soc_kwargs)
    soc.csr.locs["ddrphy"] = 23  # necessary hack I don't understand

    board.platform = soc.platform

    build_dir = os.path.join("build", "arty")

    if args.build:
        builder = Builder(soc, output_dir=build_dir,
            csr_json=os.path.join(build_dir, "csr.json"))
    else:
        builder = Builder(soc, output_dir=build_dir,
            compile_software=True, compile_gateware=False,
            csr_json=os.path.join(build_dir, "csr.json"))

    builder.build()

    # Load FPGA bitstream ----------------------------------------------------------------------
    if args.load:
        board.load(filename=os.path.join(builder.gateware_dir, soc.build_name + board.bitstream_ext))

    # Flash bitstream/images (to SPI Flash) ----------------------------------------------------
    if args.flash:
        board.flash(filename=os.path.join(builder.gateware_dir, soc.build_name + board.bitstream_ext))

INFO:SoC:Initializing ROM rom with contents (Size: 0x6418).
INFO:SoC:Auto-Resizing ROM rom from 0xfa00 to 0x6418.
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
none separate
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
adapter speed: 25000 kHz
fpga_program
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 25000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
loaded file prog/bscan_spi_xc7a35t.bit to pld device 0 in 0s 149495us
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
Error: Unknown flash device (ID 0x00ffffff)

Traceback (most recent call last):
  File "make.py", line 135, in <module>
    main()
  File "make.py", line 132, in main
    board.flash(filename=os.path.join(builder.gateware_dir, soc.build_name + board.bitstream_ext))
  File "make.py", line 27, in flash
    prog.flash(0, filename)
  File "/home/lachy/Thesis/project/locli/app/edge/soc/litex/litex/litex/build/openocd.py", line 40, in flash
    self.call(["openocd", "-f", config, "-c", script])
  File "/home/lachy/Thesis/project/locli/app/edge/soc/litex/litex/litex/build/generic_programmer.py", line 100, in call
    raise OSError(msg)
OSError: Error occured during OpenOCD's call, please check:
- OpenOCD installation.
- access permissions.
- hardware and cable.

litex-hub / zephyr-on-litex-vexriscv

Flash method since been implemented? #7