OpenSBI recently added the Hart State Management feature which changes the way secondary cpus are booted. Now instead of all the cpus entering the kernel simultaneously, the OS can boot them one at a time via a firmware call. Similar to PSCI on ARM.
One wrinkle that seems to exist is the one cpu that OpenSBI jumps into the kernel with appears random. Many times it's the first cpu but lots of times it's not. This means the kernel probably needs to be more flexible as to which is the boot cpu instead of hard coding it to zero or whatever the platform says it will be.
OpenSBI recently added the Hart State Management feature which changes the way secondary cpus are booted. Now instead of all the cpus entering the kernel simultaneously, the OS can boot them one at a time via a firmware call. Similar to PSCI on ARM.
One wrinkle that seems to exist is the one cpu that OpenSBI jumps into the kernel with appears random. Many times it's the first cpu but lots of times it's not. This means the kernel probably needs to be more flexible as to which is the boot cpu instead of hard coding it to zero or whatever the platform says it will be.