Optimizing Storage Performance with Calibrated Interrupts

After request completion, an I/O device must decide either to minimize latency by immediately firing an interrupt or to optimize for throughput by delaying the interrupt, anticipating that more requests will complete soon and help amortize the interrupt cost. Devices employ adaptive interrupt coalescing heuristics that try to balance between these opposing goals. Unfortunately, because devices lack the semantic information about which I/O requests are latency-sensitive, these heuristics can sometimes lead to disastrous results.

Instead, we propose addressing the root cause of the heuristics problem by allowing software to explicitly specify to the device if submitted requests are latency sensitive. The device then “calibrates” its interrupts to completions of latencysensitive requests. We focus on NVMe storage devices and show that it is natural to express these semantics in the kernel and the application and only requires a modest two-bit change to the device interface. Calibrated interrupts increase throughput by up to 35%, reduce CPU consumption by as much as 30%, and achieve up to 37% lower latency when interrupts are coalesced.

请求完成后，I/O 设备必须决定是通过立即触发中断来最小化延迟，还是通过延迟中断来优化吞吐量，因为预计会有更多请求很快完成，从而有助于摊销中断成本。设备采用自适应中断聚合启发式技术，试图在这些对立目标之间取得平衡。遗憾的是，由于设备缺乏有关哪些 I/O 请求对延迟敏感的语义信息，这些启发式方法有时会导致灾难性的结果。

相反，我们建议通过允许软件向设备明确说明提交的请求是否对延迟敏感，来解决启发式方法问题的根本原因。然后，设备会根据对延迟敏感的请求的完成情况 “校准 ”其中断。我们将重点放在 NVMe 存储设备上，并证明在内核和应用程序中表达这些语义是很自然的，只需要对设备接口进行适度的两比特改动即可。校准中断最多可将吞吐量提高 35%，将 CPU 消耗减少多达 30%，并在中断聚合时将延迟降低多达 37%。

liujunming / paper_reading_notes

Optimizing Storage Performance with Calibrated Interrupts #60