lix19937 / tensorrt-insight

deep insight tensorrt
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Only 11 arm cores and 4MB L3 cache observed in orin-Devkit #26

Open lix19937 opened 4 days ago

lix19937 commented 4 days ago

orin-dev@tegra-ubuntu:~$ lscpu

Architecture: aarch64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 11
On-line CPU(s) list: 0-10
Thread(s) per core: 1
Core(s) per socket: 3
Socket(s): 3
Vendor ID: ARM
Model: 1
Model name: ARMv8 Processor rev 1 (v8l)
Stepping: r0p1
BogoMIPS: 62.50
L1d cache: 704 KiB
L1i cache: 704 KiB
L2 cache: 2.8 MiB
L3 cache: 4 MiB
Vulnerability Itlb multihit: Not affected
Vulnerability L1tf: Not affected
Vulnerability Mds: Not affected
Vulnerability Meltdown: Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1: Mitigation; __user pointer sanitization
Vulnerability Spectre v2: Not affected
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Not affected
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp uscat ilrcpc flagm

Expected Behavior: 12 arm core with 6MB L3 cache

lix19937 commented 4 days ago

The Linux OS is running on top of a Type1 Hypervisor. And the hardware resources (CPU core, cache...) that can be accessed by the guest OS is allocated by the hypervisor.
Based on the current configuration, the Linux OS can only access to 11 CPU core and 4M L3 cache. This is what we expected.