Make sure variable names comply with Verilog's requirements

[lkolbly]

Some variable names cannot be allowed. For example, output is an invalid name, because it's a reserved keyword in verilog.

Other names are allowed but need to be munged. For example, we currently use names like foo_0 or foo_neg1 or foo_next. This is fine, unless somebody writes this code:

module counter_subset() -> (bits<4> counter_next) {
    bits<32> counter;
    counter[t] = counter[t-1] + 32'b1;
    counter_next[t] = counter[t][4:1];
}

which will generate:

module counter_subset (
    input[0:0] rst,
    input[0:0] clk,
    output[3:0] counter_next
);
    wire[3:0] counter_next_0;
    reg[31:0] counter_neg1;
    reg[31:0] counter_0;
    assign counter_next[3:0] = counter_next_0[3:0];
    wire[31:0] counter_next;
    assign counter_next_0 = counter_0[4:1];
    assign counter_next = counter_0[31:0] + 32'd1;
    always @(posedge clk) begin
        counter_neg1[31:0] <= counter_0[31:0];
        counter_0 <= counter_next;
    end
endmodule

Note the multiple use of counter_next. This can be avoided by doing some smart munging.